
#ifdef TSINGMA

#include "usw/include/drv_common.h"
#include "usw/include/drv_enum.h"
#include "usw/include/drv_ftm.h"
#include "usw/include/drv_ser.h"

#undef DRV_DEF_C
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F

#ifdef DRV_DEF_C
	#error DRV_DEF_C has been defined
#endif

#ifdef DRV_DEF_M
	#error DRV_DEF_M has been defined
#endif

#ifdef DRV_DEF_D
	#error DRV_DEF_D has been defined
#endif

#ifdef DRV_DEF_F
	#error DRV_DEF_F has been defined
#endif

#ifdef DRV_DEF_E
	#error DRV_DEF_E has been defined
#endif

#ifdef DRV_DEF_SDK_D
	#error DRV_DEF_SDK_D has been defined
#endif

#ifdef DRV_DEF_SDK_F
	#error DRV_DEF_SDK_F has been defined
#endif

extern tables_info_t drv_tm_tbls_list[];
 /*DS ADDR*/
#define CTC_DS_ADDR(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, TcamMem, Bus, Stats, ...) \
   static addrs_t RegName##_tbl_addrs_tm[] = {__VA_ARGS__};

 /*DS LIST*/
#define CTC_DS_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, TcamMem, Bus, Stats, ...) \
   { \
      SliceType, \
      OpType, \
      Entry, \
      0,     \
      Word*4, \
      SdbType, \
      SdbRead, \
      Bus,    \
      Stats,  \
      sizeof(RegName##_tbl_addrs_tm)/sizeof(addrs_t), \
      0, \
      sizeof(RegName##_tbl_fields_tm)/sizeof(fields_t), \
      EntryOffset*4, \
      TcamMem, \
      DRV_FEATURE_MODE_PER_CORE, \
      RegName##_t,\
      0, \
      RegName##_tbl_addrs_tm, \
      RegName##_tbl_fields_tm, \
   },

#define CTC_DS_INFO1(ModuleName, RegName, RegAlias, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, TcamMem, Bus, Stats, ...) \
    { \
    #ModuleName, \
    #RegName, \
       RegAlias##_tbl_fields_name_tm, \
    },

#define CTC_FIELD_E_INFO() \
    { \
    0, \
    0, \
    0, \
    NULL, \
    },
   
#define CTC_FIELD_E_INFO1() \
    { \
        "Invalid", \
    },

 /*Field Addr*/
#define CTC_FIELD_ADDR(ModuleName, RegName, FieldName, FullName, Bits, ...) \
  static segs_t RegName##_##FieldName##_tbl_segs_tm[] = {__VA_ARGS__};

 /*Field Info*/
#define CTC_FIELD_INFO(ModuleName, RegName, FieldName, FullName, Bits, ...) \
   { \
	  RegName##_##FieldName##_f,\
      Bits, \
      sizeof(RegName##_##FieldName##_tbl_segs_tm) / sizeof(segs_t), \
      RegName##_##FieldName##_tbl_segs_tm, \
   },

#define CTC_FIELD_INFO1(ModuleName, RegName, FieldName, FullName, Bits, ...) \
     { \
      #FullName, \
     },

 /*DS Field List Seperator*/
#define CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
 }; \
 static fields_t RegName##_tbl_fields_tm[] = {


#define DRV_DEF_C(MaxInstNum, MaxEntry, MaxWord, MaxBits,MaxStartPos,MaxSegSize)

 /* Segment Info*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName,Bits, ...)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...) \
        CTC_FIELD_ADDR(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#endif
#define DRV_DEF_E()
#define DRV_DEF_FIELD_E()
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName, FullName,Bits, ...) \
        CTC_FIELD_ADDR(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#include "usw/include/drv_ds_tm.h"
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F
#undef DRV_DEF_FIELD_E

 /* Field Info*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName,Bits, ...)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
        CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...) \
        CTC_FIELD_INFO(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#endif
#define DRV_DEF_E()
#define DRV_DEF_FIELD_E() CTC_FIELD_E_INFO()
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
        CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName,FullName, Bits, ...) \
        CTC_FIELD_INFO(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
fields_t tsingma_fields_1st = {0,0,0,NULL
#include "usw/include/drv_ds_tm.h"
};

#ifndef DRV_DS_LITE
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_DD
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F
#undef DRV_DEF_FIELD_E
#undef CTC_DS_SEPERATOR_INFO
 
#define CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
  }; \
  static fields_name_t RegName##_tbl_fields_name_tm[] = {
 
   /* Field Name Info*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(RegName, Word, No)
#define DRV_DEF_F(RegName, FieldName, No)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
          CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...) \
          CTC_FIELD_INFO1(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#endif
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
          CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName,FullName, Bits, ...) \
          CTC_FIELD_INFO1(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#define DRV_DEF_E()
#define DRV_DEF_FIELD_E() CTC_FIELD_E_INFO1()
  
  fields_name_t tm_fields_name = {NULL
#include "usw/include/drv_ds_tm.h"
  };
#endif

#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F
#undef DRV_DEF_FIELD_E

 /* DS Address*/
#define DRV_DEF_M(ModuleName, InstNum)
#define DRV_DEF_FIELD_E()
#ifdef DRV_DS_LITE
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, Bus, Stats, ...)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, Bits, ...)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, Bus, Stats, ...) \
        CTC_DS_ADDR(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, Bus, Stats, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...)
#endif
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, Bus, Stats, ...) \
        CTC_DS_ADDR(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, Bus, Stats, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...)
#define DRV_DEF_E()
#include "usw/include/drv_ds_tm.h"
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F
#undef DRV_DEF_FIELD_E

 /* DS List*/
#define DRV_DEF_M(ModuleName, InstNum)
#define DRV_DEF_FIELD_E()

#ifdef DRV_DS_LITE
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, Bits, ...)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, Bus, Stats, ...) \
        CTC_DS_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, Bus, Stats, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...)
#endif
#define DRV_DEF_E() 
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, Bus, Stats, ...) \
        CTC_DS_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, Bus, Stats, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName, Bits, ...)
tables_info_t drv_tm_tbls_list[] = {
#include "usw/include/drv_ds_tm.h"
{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,NULL,NULL}
};
#ifndef DRV_DS_LITE
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F
        
#undef DRV_DEF_DD
#undef DRV_DEF_FIELD_E

     /* DS List name*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(RegName, Word, No)
#define DRV_DEF_F(RegName, FieldName, No)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
                CTC_DS_INFO1(ModuleName, RegName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...)
#endif
#define DRV_DEF_DD(ModuleName, InstNum, RegName, RegAlias,SliceType, OpType, Entry, Word, EntryOffset, ...) \
                CTC_DS_INFO1(ModuleName, RegName, RegAlias, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
                CTC_DS_INFO1(ModuleName, RegName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName, Bits, ...)
#define DRV_DEF_E() 
#define DRV_DEF_FIELD_E()


tables_name_t drv_tm_tbls_name_list[] = {
#include "usw/include/drv_ds_tm.h"
{NULL, NULL, NULL}
};
#endif

/*ECC Interrupt*/
#define DRV_ECC_F(...)    {__VA_ARGS__},



#define TSINGMA_MCU_MUTEX0_CPU_DATA_0 0x004c0080     /*McuMutex0CpuCtl0.mutex0CpuData*/
#define TSINGMA_MCU_MUTEX0_CPU_MASK_0 0x004c0084     /*McuMutex0CpuCtl0.mutex0CpuMask*/
#define TSINGMA_MCU_MUTEX0_CPU_DATA_1 0x00540080     /*McuMutex0CpuCtl1.mutex0CpuData*/
#define TSINGMA_MCU_MUTEX0_CPU_MASK_1 0x00540084     /*McuMutex0CpuCtl1.mutex0CpuMask*/
#define TSINGMA_MCU_MUTEX0_CPU_DATA_2 0x005c0080     /*McuMutex0CpuCtl2.mutex0CpuData*/
#define TSINGMA_MCU_MUTEX0_CPU_MASK_2 0x005c0084     /*McuMutex0CpuCtl2.mutex0CpuMask*/
#define TSINGMA_MCU_MUTEX0_CPU_DATA_3 0x002c0080     /*McuMutex0CpuCtl3.mutex0CpuData*/
#define TSINGMA_MCU_MUTEX0_CPU_MASK_3 0x002c0084     /*McuMutex0CpuCtl3.mutex0CpuMask*/

#define TSINGMA_MCU_MUTEX1_CPU_DATA_0 0x004c0088     /*McuMutex1CpuCtl0.mutex0CpuData*/
#define TSINGMA_MCU_MUTEX1_CPU_MASK_0 0x004c008c     /*McuMutex1CpuCtl0.mutex0CpuMask*/
#define TSINGMA_MCU_MUTEX1_CPU_DATA_1 0x00540088     /*McuMutex1CpuCtl1.mutex0CpuData*/
#define TSINGMA_MCU_MUTEX1_CPU_MASK_1 0x0054008c     /*McuMutex1CpuCtl1.mutex0CpuMask*/
#define TSINGMA_MCU_MUTEX1_CPU_DATA_2 0x005c0088     /*McuMutex1CpuCtl2.mutex0CpuData*/
#define TSINGMA_MCU_MUTEX1_CPU_MASK_2 0x005c008c     /*McuMutex1CpuCtl2.mutex0CpuMask*/
#define TSINGMA_MCU_MUTEX1_CPU_DATA_3 0x002c0088     /*McuMutex1CpuCtl3.mutex0CpuData*/
#define TSINGMA_MCU_MUTEX1_CPU_MASK_3 0x002c008c     /*McuMutex1CpuCtl3.mutex0CpuMask*/



uint32 drv_tm_enum[DRV_CONSTANT_MAX];

uint32 drv_tm_tcam_mem_map[] =
{
    FlowTcamTcamMem_t,           /*0*/
    LpmTcamTcamMem_t,            /*1*/
    IpeCidTcamMem_t,             /*2*/
    QMgrEnqTcamMem_t,            /*3*/
    FlowTcamAdMem_t,             /*4*/
    LpmTcamAdMem_t,              /*5*/
};

drv_ecc_intr_tbl_t drv_ecc_tm_err_intr_tbl[] =
{
#include "usw/include/drv_ecc_intr_tm.h"
    {MaxTblId_t,0,0,0,0,0,0,0,0}
};

drv_ecc_sbe_cnt_t drv_ecc_tm_sbe_cnt[] =
{
    {MaxTblId_t,BufRetrvParityStatus_t,BufRetrvParityStatus_bufRetrvReassembleFifoSbeCnt_f},
    {DsBufRetrvExcp_t,BufRetrvParityStatus_t,BufRetrvParityStatus_dsBufRetrvExcpSbeCnt_f},
    {MaxTblId_t,BufRetrvParityStatus_t,BufRetrvParityStatus_miscIntfDataMemSbeCnt_f},
    {BufRetrvLinkListRam_t,BufRetrvParityStatus_t,BufRetrvParityStatus_bufRetrvLinkListRamSbeCnt_f},
    {BufRetrvPktMsgMem_t,BufRetrvParityStatus_t,BufRetrvParityStatus_bufRetrvPktMsgMemSbeCnt_f},
    {BufRetrvFirstFragRam_t,BufRetrvParityStatus_t,BufRetrvParityStatus_bufRetrvFirstFragRamSbeCnt_f},
    {BufRetrvMsgParkMem_t,BufRetrvParityStatus_t,BufRetrvParityStatus_bufRetrvMsgParkMemSbeCnt_f},
    {MaxTblId_t, BufStoreParityStatus_t,BufStoreParityStatus_bufStorePktAbortReqFifoSbeCnt_f},
    {MaxTblId_t,BufStoreParityStatus_t,BufStoreParityStatus_bufStoreIpeFreePtrFifoSbeCnt_f},
    {DsIrmPortCnt_t,BufStoreParityStatus_t,BufStoreParityStatus_dsIrmPortCntSbeCnt_f},
    {MaxTblId_t,BufStoreParityStatus_t,BufStoreParityStatus_bsMetFifoReleaseFifoSbeCnt_f},
    {BufStoreFreeListRam_t,BufStoreParityStatus_t,BufStoreParityStatus_bufStoreFreeListRamSbeCnt_f},
    {DsEgressDtls_t,CapwapProcParityStatus_t,CapwapProcParityStatus_dsEgressDtlsSbeCnt_f},
    {DsIpeCoPPCountY_t,CoppParityStatus_t,CoppParityStatus_dsIpeCoPPCountYSbeCnt_f},
    {DsIpeCoPPCountX_t,CoppParityStatus_t,CoppParityStatus_dsIpeCoPPCountXSbeCnt_f},
    {DsIpeCoPPConfig_t,CoppParityStatus_t,CoppParityStatus_dsIpeCoPPConfigSbeCnt_f},
    {Dma2AxiMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dma2AxiMemSbeCnt_f},
    {Dma1AxiMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dma1AxiMemSbeCnt_f},
    {Dma0AxiMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dma0AxiMemSbeCnt_f},
    {DmaInfoMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaInfoMemSbeCnt_f},
    {DmaWrReqDataFifo_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaWrReqDataFifoSbeCnt_f},
    {DmaUserRegMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaUserRegMemSbeCnt_f},
    {DmaDescCache_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaDescCacheSbeCnt_f},
    {MaxTblId_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaPktTxFifoSbeCnt_f},
    {DmaPktRxMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaPktRxMemSbeCnt_f},
    {DmaRegWrMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaRegWrMemSbeCnt_f},
    {DmaRegRdMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaRegRdMemSbeCnt_f},
    {DmaInfoMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaInfoMemSbeCnt_f},
    {DsAgingStatusTcam_t,DsAgingParityStatus_t,DsAgingParityStatus_dsAgingStatusTcamSbeCnt_f},
    {DsAgingStatusFib_t,DsAgingParityStatus_t,DsAgingParityStatus_dsAgingStatusFibSbeCnt_f},
    {DsAging_t,DsAgingParityStatus_t,DsAgingParityStatus_dsAgingSbeCnt_f},
    {DsElephantFlowState_t,EfdParityStatus_t,EfdParityStatus_dsElephantFlowStateSbeCnt_f},
    {DsVlanXlateDefault_t,EgrOamHashParityStatus_t,EgrOamHashParityStatus_dsVlanXlateDefaultSbeCnt_f},
    {DsDestEthLmProfile_t,EpeAclOamParityStatus_t,EpeAclOamParityStatus_dsDestEthLmProfileSbeCnt_f},
    {EpeClaPolicingSopInfoFifo_t,EpeAclOamParityStatus_t,EpeAclOamParityStatus_epeClaPolicingSopInfoRamSbeCnt_f},
    {EpeClaEopInfoFifo_t,EpeAclOamParityStatus_t,EpeAclOamParityStatus_epeClaEopInfoFifoSbeCnt_f},
    {EpeHdrAdjEopMsgFifo_t,EpeHdrAdjParityStatus_t,EpeHdrAdjParityStatus_epeHdrAdjEopMsgFifoSbeCnt_f},
    {EpeHdrAdjDataFifo_t,EpeHdrAdjParityStatus_t,EpeHdrAdjParityStatus_epeHdrAdjDataFifoSbeCnt_f},
    {DsEgressDiscardStats_t,EpeHdrEditParityStatus_t,EpeHdrEditParityStatus_dsEgressDiscardStatsSbeCnt_f},
    {EpeHdrEditPktCtlFifo_t,EpeHdrEditParityStatus_t,EpeHdrEditParityStatus_epeHdrEditPktCtlFifoSbeCnt_f},
    {DsIpv6NatPrefix_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsIpv6NatPrefixSbeCnt_f},
    {DsLatencyWatermark_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsLatencyWatermarkSbeCnt_f},
    {DsLatencyMonCnt_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsLatencyMonCntSbeCnt_f},
    {DsL3Edit6W3rd_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsL3Edit6W3rdSbeCnt_f},
    {DsL2Edit6WOuter_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsL2Edit6WOuterSbeCnt_f},
    {DsCapwapFrag_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsCapwapFragSbeCnt_f},
    {DsEgressVsi_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsEgressVsiSbeCnt_f},
    {DsEgressPortMac_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsEgressPortMacSbeCnt_f},
    {DsPortLinkAgg_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsPortLinkAggSbeCnt_f},
    {DsDestVlanStatus_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestVlanStatusSbeCnt_f},
    {DsDestVlan_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestVlanSbeCnt_f},
    {DsDestVlanProfile_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestVlanProfileSbeCnt_f},
    {DsDestStpState_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestStpStateSbeCnt_f},
    {DsGlbDestPort_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsGlbDestPortSbeCnt_f},
    {MaxTblId_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_eNHBypassInsideFifoSbeCnt_f},
    {DsVlanTagBitMap_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsVlanTagBitMapSbeCnt_f},
    {DsPortIsolation_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsPortIsolationSbeCnt_f},
    {DsEgressVlanRangeProfile_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsEgressVlanRangeProfileSbeCnt_f},
    {DsEgressRouterMac_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsEgressRouterMacSbeCnt_f},
    {DsDestPort_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestPortSbeCnt_f},
    {DsDestInterface_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestInterfaceSbeCnt_f},
    {DsDestInterfaceProfile_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestInterfaceProfileSbeCnt_f},
    {DsMacLimitThreshold_t,FibAccParityStatus_t,FibAccParityStatus_dsMacLimitThresholdSbeCnt_f},
    {DsMacLimitCount_t,FibAccParityStatus_t,FibAccParityStatus_dsMacLimitCountSbeCnt_f},
    {FlowAccAdRam0_t,FlowAccParityStatus0_t,FlowAccParityStatus0_flowAccAdRamSbeCnt_f},
    {DsIpfixSamplingCount0_t,FlowAccParityStatus0_t,FlowAccParityStatus0_dsIpfixSamplingCountSbeCnt_f},
    {DsIpfixConfig0_t,FlowAccParityStatus0_t,FlowAccParityStatus0_dsIpfixConfigSbeCnt_f},
    {FlowAccAdRam1_t,FlowAccParityStatus1_t,FlowAccParityStatus1_flowAccAdRamSbeCnt_f},
    {DsIpfixSamplingCount1_t,FlowAccParityStatus1_t,FlowAccParityStatus1_dsIpfixSamplingCountSbeCnt_f},
    {DsIpfixConfig1_t,FlowAccParityStatus1_t,FlowAccParityStatus1_dsIpfixConfigSbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamShareAd3SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamShareAd2SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamShareAd1SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamShareAd0SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd7SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd6SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd5SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd4SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd3SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd2SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd1SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeAclAd0SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeUserIdAd3SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeUserIdAd2SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeUserIdAd1SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamIpeUserIdAd0SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamEpeAclAd2SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamEpeAclAd1SbeCnt_f},
    {MaxTblId_t,FlowTcamParityStatus_t,FlowTcamParityStatus_flowTcamEpeAclAd0SbeCnt_f},
    {DsStatsQueue_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsQueueSbeCnt_f},
    {DsStats_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsSbeCnt_f},
    {DsStatsEgressGlobal3_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsEgressGlobal3SbeCnt_f},
    {DsStatsEgressGlobal2_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsEgressGlobal2SbeCnt_f},
    {DsStatsEgressGlobal1_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsEgressGlobal1SbeCnt_f},
    {DsStatsEgressGlobal0_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsEgressGlobal0SbeCnt_f},
    {DsStatsEgressACL0_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsEgressACL0SbeCnt_f},
    {DsStatsIngressGlobal3_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressGlobal3SbeCnt_f},
    {DsStatsIngressGlobal2_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressGlobal2SbeCnt_f},
    {DsStatsIngressGlobal1_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressGlobal1SbeCnt_f},
    {DsStatsIngressGlobal0_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressGlobal0SbeCnt_f},
    {DsStatsIngressACL3_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL3SbeCnt_f},
    {DsStatsIngressACL2_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL2SbeCnt_f},
    {DsStatsIngressACL1_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL1SbeCnt_f},
    {DsStatsIngressACL0_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL0SbeCnt_f},
    {MaxTblId_t,Hss28GMon_t,Hss28GMon_monHss1McuRamEccSbeCnt_f},
    {MaxTblId_t,Hss28GMon_t,Hss28GMon_monHss0McuRamEccSbeCnt_f},
    {IpeFwdExcepGroupMap_t,IpeAclParityStatus_t,IpeAclParityStatus_ipeFwdExcepGroupMapSbeCnt_f},
    {DsSrcChannel_t,IpeAclParityStatus_t,IpeAclParityStatus_dsSrcChannelSbeCnt_f},
    {DsDestMapProfileUc_t,IpeAclParityStatus_t,IpeAclParityStatus_dsDestMapProfileUcSbeCnt_f},
    {DsCategoryIdPairHashRightKey_t,IpeAclParityStatus_t,IpeAclParityStatus_dsCategoryIdPairHashRightKeySbeCnt_f},
    {DsCategoryIdPairHashLeftKey_t,IpeAclParityStatus_t,IpeAclParityStatus_dsCategoryIdPairHashLeftKeySbeCnt_f},
    {DsCategoryIdPairHashRightAd_t,IpeAclParityStatus_t,IpeAclParityStatus_dsCategoryIdPairHashRightAdSbeCnt_f},
    {DsCategoryIdPairHashLeftAd_t,IpeAclParityStatus_t,IpeAclParityStatus_dsCategoryIdPairHashLeftAdSbeCnt_f},
    {DsCategoryIdPairTcamAd_t,IpeAclParityStatus_t,IpeAclParityStatus_dsCategoryIdPairTcamAdSbeCnt_f},
    {DsAclVlanActionProfile_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAclVlanActionProfileSbeCnt_f},
    {DsCFlexSrcPortBlockMask_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsCFlexSrcPortBlockMaskSbeCnt_f},
    {DsIpePhbMutationCosMap_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsIpePhbMutationCosMapSbeCnt_f},
    {DsIpePhbMutationDscpMap_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsIpePhbMutationDscpMapSbeCnt_f},
    {DsEcmpMember_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsEcmpMemberSbeCnt_f},
    {DsEcmpGroup_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsEcmpGroupSbeCnt_f},
    {DsVlanActionProfile_t,IpeHdrAdjParityStatus_t,IpeHdrAdjParityStatus_dsVlanActionProfileSbeCnt_f},
    {DsVlanRangeProfile_t,IpeHdrAdjParityStatus_t,IpeHdrAdjParityStatus_dsVlanRangeProfileSbeCnt_f},
    {DsPhyPortExt_t,IpeHdrAdjParityStatus_t,IpeHdrAdjParityStatus_dsPhyPortExtSbeCnt_f},
    {DsPhyPort_t,IpeHdrAdjParityStatus_t,IpeHdrAdjParityStatus_dsPhyPortSbeCnt_f},
    {DsSrcStpState_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcStpStateSbeCnt_f},
    {DsSrcVlanProfile_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcVlanProfileSbeCnt_f},
    {DsSrcVlanStatus_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcVlanStatusSbeCnt_f},
    {DsSrcVlan_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcVlanSbeCnt_f},
    {DsVlan2Ptr_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsVlan2PtrSbeCnt_f},
    {DsSrcInterfaceProfile_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcInterfaceProfileSbeCnt_f},
    {DsSrcInterface_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcInterfaceSbeCnt_f},
    {DsSrcPort_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcPortSbeCnt_f},
    {DsRouterMac_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsRouterMacSbeCnt_f},
    {DsRouterMacInner_t,IpeLkupMgrParityStatus_t,IpeLkupMgrParityStatus_dsRouterMacInnerSbeCnt_f},
    {DsSrcEthLmProfile_t,IpePktProcParityStatus_t,IpePktProcParityStatus_dsSrcEthLmProfileSbeCnt_f},
    {IpePhbDscpMap_t,IpePktProcParityStatus_t,IpePktProcParityStatus_ipePhbDscpMapSbeCnt_f},
    {DsBidiPimGroup_t,IpePktProcParityStatus_t,IpePktProcParityStatus_dsBidiPimGroupSbeCnt_f},
    {DsRpf_t,IpePktProcParityStatus_t,IpePktProcParityStatus_dsRpfSbeCnt_f},
    {DsVrf_t,IpePktProcParityStatus_t,IpePktProcParityStatus_dsVrfSbeCnt_f},
    {DsVsi_t,IpePktProcParityStatus_t,IpePktProcParityStatus_dsVsiSbeCnt_f},
    {DsPortBasedHashProfile1_t,LinkAggParityStatus_t,LinkAggParityStatus_dsPortBasedHashProfile1SbeCnt_f},
    {DsSgmacMap_t,LinkAggParityStatus_t,LinkAggParityStatus_dsSgmacMapSbeCnt_f},
    {DsLinkAggregateChannelMemberSet_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregateChannelMemberSetSbeCnt_f},
    {DsLinkAggregateMemberSet_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregateMemberSetSbeCnt_f},
    {DsLinkAggregationPortChannelMap_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregationPortChannelMapSbeCnt_f},
    {DsLinkAggregateChannelMember_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregateChannelMemberSbeCnt_f},
    {DsLinkAggregateMember_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregateMemberSbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd5SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd4SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd3SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd2SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd1SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd0SbeCnt_f},
    {DsDot1AePnCheck_t,MacSecEngineParityStatus_t,MacSecEngineParityStatus_dsDot1AePnCheckSbeCnt_f},
    {DsDot1AeDecryptConfig_t,MacSecEngineParityStatus_t,MacSecEngineParityStatus_dsDot1AeDecryptConfigSbeCnt_f},
    {DsDot1AeSci_t,MacSecEngineParityStatus_t,MacSecEngineParityStatus_dsDot1AeSciSbeCnt_f},
    {DsDot1AeAesKey_t,MacSecEngineParityStatus_t,MacSecEngineParityStatus_dsDot1AeAesKeySbeCnt_f},
    //{MaxTblId_t,McuSupStats0_t,McuSupStats0_mcuSupDataMemSbeCnt_f},
    //{MaxTblId_t,McuSupStats1_t,McuSupStats1_mcuSupDataMemSbeCnt_f},
    //{MaxTblId_t,McuSupStats2_t,McuSupStats2_mcuSupDataMemSbeCnt_f},
    //{MaxTblId_t,McuSupStats3_t,McuSupStats3_mcuSupDataMemSbeCnt_f},
    //{MaxTblId_t,McuSupStats0_t,McuSupStats0_mcuSupProgMemSbeCnt_f},
    //{MaxTblId_t,McuSupStats1_t,McuSupStats1_mcuSupProgMemSbeCnt_f},
    //{MaxTblId_t,McuSupStats2_t,McuSupStats2_mcuSupProgMemSbeCnt_f},
    //{MaxTblId_t,McuSupStats3_t,McuSupStats3_mcuSupProgMemSbeCnt_f},
    {MetMcastHiRcdFifo_t,MetFifoParityStatus_t,MetFifoParityStatus_metMcastHiRcdFifoSbeCnt_f},
    {MetMcastLoRcdFifo_t,MetFifoParityStatus_t,MetFifoParityStatus_metMcastLoRcdFifoSbeCnt_f},
    {MaxTblId_t,MetFifoParityStatus_t,MetFifoParityStatus_metMcastLoLoopFifoSbeCnt_f},
    {MaxTblId_t,MetFifoParityStatus_t,MetFifoParityStatus_metMcastHiLoopFifoSbeCnt_f},
    {DsApsBridge_t,MetFifoParityStatus_t,MetFifoParityStatus_dsApsBridgeSbeCnt_f},
    {MaxTblId_t,MetFifoParityStatus_t,MetFifoParityStatus_metLogReqFifoSbeCnt_f},
    {DsDestMapProfileMc_t,MetFifoParityStatus_t,MetFifoParityStatus_dsDestMapProfileMcSbeCnt_f},
    {MetUcastLoRcdFifo_t,MetFifoParityStatus_t,MetFifoParityStatus_metUcastLoRcdFifoSbeCnt_f},
    {MetUcastHiRcdFifo_t,MetFifoParityStatus_t,MetFifoParityStatus_metUcastHiRcdFifoSbeCnt_f},
    {DsMetLinkAggregatePort_t,MetFifoParityStatus_t,MetFifoParityStatus_dsMetLinkAggregatePortSbeCnt_f},
    {DsMetLinkAggregateBitmap_t,MetFifoParityStatus_t,MetFifoParityStatus_dsMetLinkAggregateBitmapSbeCnt_f},
    {MetRcdMem_t,MetFifoParityStatus_t,MetFifoParityStatus_metRcdMemSbeCnt_f},
    {MetMsgMem_t,MetFifoParityStatus_t,MetFifoParityStatus_metMsgMemSbeCnt_f},
    {MetMcastTrackFifo_t,MetFifoParityStatus_t,MetFifoParityStatus_metMcastTrackFifoSbeCnt_f},
    {DsMetFifoExcp_t,MetFifoParityStatus_t,MetFifoParityStatus_dsMetFifoExcpSbeCnt_f},
    {MetEnqRcdFifo_t,MetFifoParityStatus_t,MetFifoParityStatus_metEnqRcdFifoSbeCnt_f},
    {MetBrRcdFifo_t,MetFifoParityStatus_t,MetFifoParityStatus_metBrRcdFifoSbeCnt_f},
    {DsMplsHashCamAd_t,MplsHashParityStatus_t,MplsHashParityStatus_dsMplsHashCamAdSbeCnt_f},
    {MaxTblId_t,MplsHashParityStatus_t,MplsHashParityStatus_mplsHashAdSbeCnt_f},
    {MaxTblId_t,NetRxParityStatus_t,NetRxParityStatus_netRxFreePtr1FifoSbeCnt_f},
    {MaxTblId_t,NetRxParityStatus_t,NetRxParityStatus_netRxFreePtr0FifoSbeCnt_f},
    {DsChannelizeMode_t,NetRxParityStatus_t,NetRxParityStatus_dsChannelizeModeSbeCnt_f},
    {MaxTblId_t,NetRxParityStatus_t,NetRxParityStatus_netRxFreePtr3FifoSbeCnt_f},
    {MaxTblId_t,NetRxParityStatus_t,NetRxParityStatus_netRxFreePtr2FifoSbeCnt_f},
    {NetTxPktHdr3_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr3SbeCnt_f},
    {NetTxPktHdr2_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr2SbeCnt_f},
    {NetTxPktHdr1_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr1SbeCnt_f},
    {NetTxPktHdr0_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr0SbeCnt_f},
    {OamParserPktFifo_t,OamParserParityStatus_t,OamParserParityStatus_oamParserPktFifoSbeCnt_f},
    {MaxTblId_t,PbCtlParityStatus_t,PbCtlParityStatus_pbCtlPktBufRRamSbeCnt_f},
    {DsEpePolicing1CountY_t,PolicingEpeParityStatus_t,PolicingEpeParityStatus_dsEpePolicing1CountYSbeCnt_f},
    {DsEpePolicing1CountX_t,PolicingEpeParityStatus_t,PolicingEpeParityStatus_dsEpePolicing1CountXSbeCnt_f},
    {DsEpePolicing1Config_t,PolicingEpeParityStatus_t,PolicingEpeParityStatus_dsEpePolicing1ConfigSbeCnt_f},
    {DsEpePolicing0CountY_t,PolicingEpeParityStatus_t,PolicingEpeParityStatus_dsEpePolicing0CountYSbeCnt_f},
    {DsEpePolicing0CountX_t,PolicingEpeParityStatus_t,PolicingEpeParityStatus_dsEpePolicing0CountXSbeCnt_f},
    {DsEpePolicing0Config_t,PolicingEpeParityStatus_t,PolicingEpeParityStatus_dsEpePolicing0ConfigSbeCnt_f},
    {DsIpePolicing1ProfileY_t,PolicingIpeParityStatus_t,PolicingIpeParityStatus_dsIpePolicing1ProfileYSbeCnt_f},
    {DsIpePolicing1ProfileX_t,PolicingIpeParityStatus_t,PolicingIpeParityStatus_dsIpePolicing1ProfileXSbeCnt_f},
    {DsIpePolicing1CountY_t,PolicingIpeParityStatus_t,PolicingIpeParityStatus_dsIpePolicing1CountYSbeCnt_f},
    {DsIpePolicing1CountX_t,PolicingIpeParityStatus_t,PolicingIpeParityStatus_dsIpePolicing1CountXSbeCnt_f},
    {DsIpePolicing1Config_t,PolicingIpeParityStatus_t,PolicingIpeParityStatus_dsIpePolicing1ConfigSbeCnt_f},
    {DsIpePolicing0CountY_t,PolicingIpeParityStatus_t,PolicingIpeParityStatus_dsIpePolicing0CountYSbeCnt_f},
    {DsIpePolicing0CountX_t,PolicingIpeParityStatus_t,PolicingIpeParityStatus_dsIpePolicing0CountXSbeCnt_f},
    {DsIpePolicing0Config_t,PolicingIpeParityStatus_t,PolicingIpeParityStatus_dsIpePolicing0ConfigSbeCnt_f},
    {DsIpePolicing0ProfileY_t,PolicingIpeParityStatus_t,PolicingIpeParityStatus_dsIpePolicing0ProfileYSbeCnt_f},
    {DsIpePolicing0ProfileX_t,PolicingIpeParityStatus_t,PolicingIpeParityStatus_dsIpePolicing0ProfileXSbeCnt_f},
    {DsQMgrNetBaseQueMeterProfile_t,QMgrDeqParityStatus_t,QMgrDeqParityStatus_dsQMgrNetBaseQueMeterProfileSbeCnt_f},
    {DsQMgrNetBaseQueMeterProfId_t,QMgrDeqParityStatus_t,QMgrDeqParityStatus_dsQMgrNetBaseQueMeterProfIdSbeCnt_f},
    {DsQMgrExtGrpShpProfId_t,QMgrDeqParityStatus_t,QMgrDeqParityStatus_dsQMgrExtGrpShpProfIdSbeCnt_f},
    {DsQMgrExtQueShpProfId_t,QMgrDeqParityStatus_t,QMgrDeqParityStatus_dsQMgrExtQueShpProfIdSbeCnt_f},
    {DsQMgrNetQueShpProfile_t,QMgrDeqParityStatus_t,QMgrDeqParityStatus_dsQMgrNetQueShpProfileSbeCnt_f},
    {DsQMgrNetQueShpProfId_t,QMgrDeqParityStatus_t,QMgrDeqParityStatus_dsQMgrNetQueShpProfIdSbeCnt_f},
    {DsQMgrNetChanShpToken_t,QMgrDeqParityStatus_t,QMgrDeqParityStatus_dsQMgrNetChanShpTokenSbeCnt_f},
    {DsQMgrExtGrpShpProfile_t,QMgrDeqParityStatus_t,QMgrDeqParityStatus_dsQMgrExtGrpShpProfileSbeCnt_f},
    {DsQMgrExtSchMap_t,QMgrDeqParityStatus_t,QMgrDeqParityStatus_dsQMgrExtSchMap1SbeCnt_f},
    {DsQMgrBaseSchMap_t,QMgrDeqParityStatus_t,QMgrDeqParityStatus_dsQMgrBaseSchMap1SbeCnt_f},
    {DsErmResrcMonPortMax_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsErmResrcMonPortMaxSbeCnt_f},
    {DsErmQueueCfg_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsErmQueueCfgSbeCnt_f},
    {DsPortBlockMask_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsPortBlockMaskSbeCnt_f},
    {DsQueueMapTcamData_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsQueueMapTcamDataSbeCnt_f},
    {DsCFlexDstChannelBlockMask_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsCFlexDstChannelBlockMaskSbeCnt_f},
    {DsErmAqmQueueStatus_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsErmAqmQueueStatusSbeCnt_f},
    {DsErmAqmQueueCfg_t,QMgrEnqParityStatus_t,QMgrEnqParityStatus_dsErmAqmQueueCfgSbeCnt_f},
    {DsQueueEntry_t,QMgrMsgStoreParityStatus_t,QMgrMsgStoreParityStatus_dsQueueEntrySbeCnt_f},
    {DsQMsgUsedList_t,QMgrMsgStoreParityStatus_t,QMgrMsgStoreParityStatus_dsQMsgUsedListSbeCnt_f},
    {DsMsgFreePtr_t,QMgrMsgStoreParityStatus_t,QMgrMsgStoreParityStatus_dsMsgFreePtrSbeCnt_f},
    {MaxTblId_t,ShareBufferParityStatus_t,ShareBufferParityStatus_shareBufRam6RdDataSbeCnt_f},
    {MaxTblId_t,ShareBufferParityStatus_t,ShareBufferParityStatus_shareBufRam5RdData1SbeCnt_f},
    {MaxTblId_t,ShareBufferParityStatus_t,ShareBufferParityStatus_shareBufRam5RdData0SbeCnt_f},
    {MaxTblId_t,ShareBufferParityStatus_t,ShareBufferParityStatus_shareBufRam4RdData1SbeCnt_f},
    {MaxTblId_t,ShareBufferParityStatus_t,ShareBufferParityStatus_shareBufRam4RdData0SbeCnt_f},
    {MaxTblId_t,ShareBufferParityStatus_t,ShareBufferParityStatus_shareBufRam3RdData1SbeCnt_f},
    {MaxTblId_t,ShareBufferParityStatus_t,ShareBufferParityStatus_shareBufRam3RdData0SbeCnt_f},
    {MaxTblId_t,ShareBufferParityStatus_t,ShareBufferParityStatus_shareBufRam2RdData1SbeCnt_f},
    {MaxTblId_t,ShareBufferParityStatus_t,ShareBufferParityStatus_shareBufRam2RdData0SbeCnt_f},
    {MaxTblId_t,ShareBufferParityStatus_t,ShareBufferParityStatus_shareBufRam1RdData1SbeCnt_f},
    {MaxTblId_t,ShareBufferParityStatus_t,ShareBufferParityStatus_shareBufRam1RdData0SbeCnt_f},
    {MaxTblId_t,ShareBufferParityStatus_t,ShareBufferParityStatus_shareBufRam0RdData1SbeCnt_f},
    {MaxTblId_t,ShareBufferParityStatus_t,ShareBufferParityStatus_shareBufRam0RdData0SbeCnt_f},
    {DsIpeStormCtl0ProfileX_t,StormCtlParityStatus_t,StormCtlParityStatus_dsIpeStormCtl0ProfileXSbeCnt_f},
    {DsIpeStormCtl0ProfileY_t,StormCtlParityStatus_t,StormCtlParityStatus_dsIpeStormCtl0ProfileYSbeCnt_f},
    {DsIpeStormCtl0Config_t,StormCtlParityStatus_t,StormCtlParityStatus_dsIpeStormCtl0ConfigSbeCnt_f},
    {DsIpeStormCtl0CountX_t,StormCtlParityStatus_t,StormCtlParityStatus_dsIpeStormCtl0CountXSbeCnt_f},
    {DsIpeStormCtl0CountY_t,StormCtlParityStatus_t,StormCtlParityStatus_dsIpeStormCtl0CountYSbeCnt_f},
    {DsIpeStormCtl1Config_t,StormCtlParityStatus_t,StormCtlParityStatus_dsIpeStormCtl1ConfigSbeCnt_f},
    {DsIpeStormCtl1CountX_t,StormCtlParityStatus_t,StormCtlParityStatus_dsIpeStormCtl1CountXSbeCnt_f},
    {DsIpeStormCtl1CountY_t,StormCtlParityStatus_t,StormCtlParityStatus_dsIpeStormCtl1CountYSbeCnt_f},
    {DsIpeStormCtl1ProfileX_t,StormCtlParityStatus_t,StormCtlParityStatus_dsIpeStormCtl1ProfileXSbeCnt_f},
    {DsIpeStormCtl1ProfileY_t,StormCtlParityStatus_t,StormCtlParityStatus_dsIpeStormCtl1ProfileYSbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t, DynamicAdParityStatus_shareAdRam5SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t, DynamicAdParityStatus_shareAdRam4SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t, DynamicAdParityStatus_shareAdRam3SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t, DynamicAdParityStatus_shareAdRam2SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t, DynamicAdParityStatus_shareAdRam1SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t, DynamicAdParityStatus_shareAdRam0SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam5SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam4SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam3SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam2SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam1SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam0SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t, DynamicKeyParityStatus_shareKeyRam10SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t, DynamicKeyParityStatus_shareKeyRam9SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t, DynamicKeyParityStatus_shareKeyRam8SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t, DynamicKeyParityStatus_shareKeyRam7SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t, DynamicKeyParityStatus_shareKeyRam6SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t, DynamicKeyParityStatus_shareKeyRam5SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t, DynamicKeyParityStatus_shareKeyRam4SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t, DynamicKeyParityStatus_shareKeyRam3SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t, DynamicKeyParityStatus_shareKeyRam2SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t, DynamicKeyParityStatus_shareKeyRam1SbeCnt_f},
    {MaxTblId_t,DynamicKeyParityStatus_t, DynamicKeyParityStatus_shareKeyRam0SbeCnt_f},
    {MaxTblId_t, MaxTblId_t, 0}
};


uint16 drv_ecc_tm_scan_tcam_tbl[][5] =
{
    {DRV_FTM_TCAM_KEY0,DsAclQosMacKey160Egr0_t,DsAclQosMacKey160Egr1_t,DsAclQosMacKey160Egr2_t,MaxTblId_t},
    {DRV_FTM_TCAM_KEY0,DsAclQosMacKey160Ing0_t,DsAclQosMacKey160Ing1_t,DsAclQosMacKey160Ing2_t,DsAclQosMacKey160Ing3_t},
    {DRV_FTM_TCAM_KEY0,DsAclQosMacKey160Ing4_t,DsAclQosMacKey160Ing5_t,DsAclQosMacKey160Ing6_t,DsAclQosMacKey160Ing7_t},
    {DRV_FTM_TCAM_KEY0,DsUserId0TcamKey160_t,DsUserId1TcamKey160_t,MaxTblId_t,MaxTblId_t},
    {DRV_FTM_LPM_TCAM_KEY0,DsLpmTcamIpv4HalfKey_t,MaxTblId_t ,MaxTblId_t,MaxTblId_t},
    {DRV_FTM_CID_TCAM,DsCategoryIdPairTcamKey_t,MaxTblId_t,MaxTblId_t,MaxTblId_t},
    {DRV_FTM_QUEUE_TCAM,DsQueueMapTcamKey_t,MaxTblId_t,MaxTblId_t,MaxTblId_t},
    {MaxTblId_t,MaxTblId_t,MaxTblId_t,MaxTblId_t,MaxTblId_t}
};

#define DRV_MEM_REG(name, id, num, addr3w, addr6w, addr12w, E_SZ, ADD_SEL) \
    do{\
        p_drv_master[lchip]->p_mem_info[id].entry_num = num;\
        p_drv_master[lchip]->p_mem_info[id].addr_3w = addr3w;\
        p_drv_master[lchip]->p_mem_info[id].addr_6w = addr6w;\
        p_drv_master[lchip]->p_mem_info[id].addr_12w = addr12w;\
        p_drv_master[lchip]->p_mem_info[id].entry_size = E_SZ<<2;\
        p_drv_master[lchip]->p_mem_info[id].addr_sel = ADD_SEL;\
        p_drv_master[lchip]->p_mem_info[id].index_map = NULL;\
     }while(0)
#define DRV_MEM_REG_TCAM(name, id, SUB_ID, num, addr3w, addr6w, addr12w, TMID) \
    do{\
        p_drv_master[lchip]->p_mem_info[id].entry_num = num;\
        p_drv_master[lchip]->p_mem_info[id].addr_3w = addr3w;\
        p_drv_master[lchip]->p_mem_info[id].addr_6w = addr6w;\
        p_drv_master[lchip]->p_mem_info[id].addr_12w = addr12w;\
        p_drv_master[lchip]->p_mem_info[id].tcam_map_id = TMID;\
        p_drv_master[lchip]->p_mem_info[id].sub_id = SUB_ID;\
        p_drv_master[lchip]->p_mem_info[id].index_map = NULL;\
     }while(0)

int32
drv_mem_init_tsingma(uint8 lchip)
{
    DRV_MEM_REG("KeyRam0",    DRV_FTM_SRAM0,  16384, 0xa800000, 0xa000000, 0xb000000, 12, 2);
    DRV_MEM_REG("KeyRam1",    DRV_FTM_SRAM1,  16384, 0xa880000, 0xa080000, 0xb080000, 12, 2);
    DRV_MEM_REG("KeyRam2",    DRV_FTM_SRAM2,  16384, 0xa900000, 0xa100000, 0xb100000, 12, 2);
    DRV_MEM_REG("KeyRam3",    DRV_FTM_SRAM3,  8192,  0xa980000, 0xa180000, 0xb180000, 12, 2);
    DRV_MEM_REG("KeyRam4",    DRV_FTM_SRAM4,  8192,  0xaa00000, 0xa200000, 0xb200000, 12, 2);
    DRV_MEM_REG("KeyRam5",    DRV_FTM_SRAM5,  4096,  0xaa80000, 0xa280000, 0xb280000, 12, 2);
    DRV_MEM_REG("KeyRam6",    DRV_FTM_SRAM6,  8192,  0xab00000, 0xa300000, 0xb300000, 12, 2);
    DRV_MEM_REG("KeyRam7",    DRV_FTM_SRAM7,  8192,  0xab80000, 0xa380000, 0xb380000, 12, 2);
    DRV_MEM_REG("KeyRam8",    DRV_FTM_SRAM8,  8192,  0xac00000, 0xa400000, 0xb400000, 12, 2);
    DRV_MEM_REG("KeyRam9",    DRV_FTM_SRAM9,  8192,  0xac80000, 0xa480000, 0xb480000, 12, 2);
    DRV_MEM_REG("KeyRam10",   DRV_FTM_SRAM10, 8192,  0xad00000, 0xa500000, 0xb500000, 12, 2);
    DRV_MEM_REG("AdRam0",     DRV_FTM_SRAM11, 16384, 0x5800000, 0x5000000, 0x5400000, 12, 2);
    DRV_MEM_REG("AdRam1",     DRV_FTM_SRAM12, 8192,  0x5880000, 0x5080000, 0x5480000, 12, 2);
    DRV_MEM_REG("AdRam2",     DRV_FTM_SRAM13, 8192,  0x5900000, 0x5100000, 0x5500000, 12, 2);
    DRV_MEM_REG("AdRam3",     DRV_FTM_SRAM14, 16384, 0x5980000, 0x5180000, 0x5580000, 12, 2);
    DRV_MEM_REG("AdRam4",     DRV_FTM_SRAM15, 8192,  0x5a00000, 0x5200000, 0x5600000, 12, 2);
    DRV_MEM_REG("AdRam5",     DRV_FTM_SRAM16, 8192,  0x5a80000, 0x5280000, 0x5680000, 12, 2);
    DRV_MEM_REG("EditRam0",   DRV_FTM_SRAM17, 32768, 0x3000000, 0x3400000, 0x3800000, 12, 2);
    DRV_MEM_REG("EditRam1",   DRV_FTM_SRAM18, 8192,  0x3080000, 0x3480000, 0x3880000, 12, 2);
    DRV_MEM_REG("EditRam2",   DRV_FTM_SRAM19, 8192,  0x3100000, 0x3500000, 0x3900000, 12, 2);
    DRV_MEM_REG("EditRam3",   DRV_FTM_SRAM20, 4096,  0x3180000, 0x3580000, 0x3980000, 12, 2);
    DRV_MEM_REG("EditRam4",   DRV_FTM_SRAM21, 4096,  0x3200000, 0x3600000, 0x3a00000, 12, 2);
    DRV_MEM_REG("EditRam5",   DRV_FTM_SRAM22, 4096,  0x3280000, 0x3680000, 0x3a80000, 12, 2);
    DRV_MEM_REG("SharedRam0", DRV_FTM_SRAM23, 32768, 0x7000000, 0x0, 	   0x0,       3, 0);
    DRV_MEM_REG("SharedRam1", DRV_FTM_SRAM24, 32768, 0x7100000, 0x0,       0x0,       3, 0);
    DRV_MEM_REG("SharedRam2", DRV_FTM_SRAM25, 32768, 0x7200000, 0x0,       0x0,       3, 0);
    DRV_MEM_REG("SharedRam3", DRV_FTM_SRAM26, 32768, 0x7300000, 0x0,       0x0,       3, 0);
    DRV_MEM_REG("SharedRam4", DRV_FTM_SRAM27, 32768, 0x7400000, 0x0,       0x0,       3, 0);
    DRV_MEM_REG("SharedRam5", DRV_FTM_SRAM28, 32768, 0x7500000, 0,         0x0,       3, 0);
    DRV_MEM_REG("SharedRam6", DRV_FTM_SRAM29, 32768, 0x7600000, 0x7800000, 0x0,       6, 1);
    DRV_MEM_REG("MplsRam0",   DRV_FTM_MIXED0, 4096,  0x1d00000, 0x0,       0x0,       8,  0);
    DRV_MEM_REG("MplsRam1",   DRV_FTM_MIXED1, 4096,  0x1d10000, 0x0,       0x0,       8,  0);
    DRV_MEM_REG("MplsRam2",   DRV_FTM_MIXED2, 8192,  0x1c00000, 0x1c80000, 0x0,       6,  1);
    DRV_MEM_REG_TCAM("Tcam key0",  DRV_FTM_TCAM_KEY0,  0, 1024, 0x2400000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key1",  DRV_FTM_TCAM_KEY1,  1, 1024, 0x2410000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key2",  DRV_FTM_TCAM_KEY2,  2, 1024, 0x2420000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key3",  DRV_FTM_TCAM_KEY3,  3, 1024, 0x2430000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key4",  DRV_FTM_TCAM_KEY4,  4, 1024, 0x2440000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key5",  DRV_FTM_TCAM_KEY5,  5, 1024, 0x2450000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key6",  DRV_FTM_TCAM_KEY6,  6, 1024, 0x2460000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key7",  DRV_FTM_TCAM_KEY7,  7, 1024, 0x2470000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key8",  DRV_FTM_TCAM_KEY8,  8, 1024, 0x2480000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key9",  DRV_FTM_TCAM_KEY9,  9, 1024, 0x2490000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key10", DRV_FTM_TCAM_KEY10, 10, 1024, 0x24a0000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key11", DRV_FTM_TCAM_KEY11, 11, 1024, 0x24b0000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key12", DRV_FTM_TCAM_KEY12, 12, 1024, 0x24c0000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key13", DRV_FTM_TCAM_KEY13, 13, 1024, 0x24d0000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key14", DRV_FTM_TCAM_KEY14, 14, 1024, 0x24e0000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key15", DRV_FTM_TCAM_KEY15, 15, 2048, 0x24f0000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key16", DRV_FTM_TCAM_KEY16, 16, 2048, 0x2500000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key17", DRV_FTM_TCAM_KEY17, 17, 2048, 0x2510000, 0x0, 0x0, 0);
    DRV_MEM_REG_TCAM("Tcam key18", DRV_FTM_TCAM_KEY18, 18, 2048, 0x2520000, 0x0, 0x0, 0);
    DRV_MEM_REG("Tcam AD0",  DRV_FTM_TCAM_AD0,  1024, 0x2600000, 0x2600000, 0x2600000, 6, 0);
    DRV_MEM_REG("Tcam AD1",  DRV_FTM_TCAM_AD1,  1024, 0x2608000, 0x2608000, 0x2608000, 6, 0);
    DRV_MEM_REG("Tcam AD2",  DRV_FTM_TCAM_AD2,  1024, 0x2610000, 0x2610000, 0x2610000, 6, 0);
    DRV_MEM_REG("Tcam AD3",  DRV_FTM_TCAM_AD3,  1024, 0x2618000, 0x2618000, 0x2618000, 6, 0);
    DRV_MEM_REG("Tcam AD4",  DRV_FTM_TCAM_AD4,  1024, 0x2620000, 0x2620000, 0x2620000, 6, 0);
    DRV_MEM_REG("Tcam AD5",  DRV_FTM_TCAM_AD5,  1024, 0x2628000, 0x2628000, 0x2628000, 6, 0);
    DRV_MEM_REG("Tcam AD6",  DRV_FTM_TCAM_AD6,  1024, 0x2630000, 0x2630000, 0x2630000, 6, 0);
    DRV_MEM_REG("Tcam AD7",  DRV_FTM_TCAM_AD7,  1024, 0x2638000, 0x2638000, 0x2638000, 6, 0);
    DRV_MEM_REG("Tcam AD8",  DRV_FTM_TCAM_AD8,  1024, 0x2640000, 0x2640000, 0x2640000, 6, 0);
    DRV_MEM_REG("Tcam AD9",  DRV_FTM_TCAM_AD9,  1024, 0x2648000, 0x2648000, 0x2648000, 6, 0);
    DRV_MEM_REG("Tcam AD10", DRV_FTM_TCAM_AD10, 1024, 0x2650000, 0x2650000, 0x2650000, 6, 0);
    DRV_MEM_REG("Tcam AD11", DRV_FTM_TCAM_AD11, 1024, 0x2658000, 0x2658000, 0x2658000, 6, 0);
    DRV_MEM_REG("Tcam AD12", DRV_FTM_TCAM_AD12, 1024, 0x2660000, 0x2660000, 0x2660000, 6, 0);
    DRV_MEM_REG("Tcam AD13", DRV_FTM_TCAM_AD13, 1024, 0x2668000, 0x2668000, 0x2668000, 6, 0);
    DRV_MEM_REG("Tcam AD14", DRV_FTM_TCAM_AD14, 1024, 0x2670000, 0x2670000, 0x2670000, 6, 0);
    DRV_MEM_REG("Tcam AD15", DRV_FTM_TCAM_AD15, 2048, 0x2678000, 0x2678000, 0x2678000, 6, 0);
    DRV_MEM_REG("Tcam AD16", DRV_FTM_TCAM_AD16, 2048, 0x2680000, 0x2680000, 0x2680000, 6, 0);
    DRV_MEM_REG("Tcam AD17", DRV_FTM_TCAM_AD17, 2048, 0x2688000, 0x2688000, 0x2688000, 6, 0);
    DRV_MEM_REG("Tcam AD18", DRV_FTM_TCAM_AD18, 2048, 0x2690000, 0x2690000, 0x2690000, 6, 0);
    #ifdef EMULATION_ENV
    DRV_MEM_REG_TCAM("LPM Tcam key0" ,  DRV_FTM_LPM_TCAM_KEY0,  0, 32, 0x4100000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key1" ,  DRV_FTM_LPM_TCAM_KEY1,  1, 0,  0x4102000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key2" ,  DRV_FTM_LPM_TCAM_KEY2,  2, 32, 0x4104000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key3" ,  DRV_FTM_LPM_TCAM_KEY3,  3, 0,  0x4106000, 0x0, 0x0, 1);

    DRV_MEM_REG_TCAM("LPM Tcam key4" ,  DRV_FTM_LPM_TCAM_KEY4,  4, 32, 0x4120000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key5" ,  DRV_FTM_LPM_TCAM_KEY5,  5, 0,  0x4122000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key6" ,  DRV_FTM_LPM_TCAM_KEY6,  6, 32, 0x4124000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key7" ,  DRV_FTM_LPM_TCAM_KEY7,  7, 0,  0x4126000, 0x0, 0x0, 1);

    DRV_MEM_REG_TCAM("LPM Tcam key8" ,  DRV_FTM_LPM_TCAM_KEY8,  8, 32, 0x4140000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key9" ,  DRV_FTM_LPM_TCAM_KEY9,  9, 0,  0x4148000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key10" , DRV_FTM_LPM_TCAM_KEY10, 10, 32, 0x4150000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key11" , DRV_FTM_LPM_TCAM_KEY11, 11, 0,  0x4158000, 0x0, 0x0, 1);


    DRV_MEM_REG("LPM Tcam Ad0" ,  DRV_FTM_LPM_TCAM_AD0,  32, 0x4180000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad1" ,  DRV_FTM_LPM_TCAM_AD1,  0,  0x4182000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad2" ,  DRV_FTM_LPM_TCAM_AD2,  32, 0x4184000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad3" ,  DRV_FTM_LPM_TCAM_AD3,  0,  0x4186000, 0x0, 0x0, 2, 0);

    DRV_MEM_REG("LPM Tcam Ad4" ,  DRV_FTM_LPM_TCAM_AD4,  32, 0x4190000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad5" ,  DRV_FTM_LPM_TCAM_AD5,  0,  0x4192000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad6" ,  DRV_FTM_LPM_TCAM_AD6,  32, 0x4194000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad7" ,  DRV_FTM_LPM_TCAM_AD7,  0,  0x4196000, 0x0, 0x0, 2, 0);

    DRV_MEM_REG("LPM Tcam Ad8" ,  DRV_FTM_LPM_TCAM_AD8,  32, 0x41a0000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad9" ,  DRV_FTM_LPM_TCAM_AD9,  0,  0x41a4000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad10" , DRV_FTM_LPM_TCAM_AD10, 32, 0x41a8000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad11" , DRV_FTM_LPM_TCAM_AD11, 0,  0x41ac000, 0x0, 0x0, 2, 0);

    DRV_MEM_REG_TCAM("Queue Tcam"    ,  DRV_FTM_QUEUE_TCAM, 0, 32, 0x00644000, 0xb1000000, 0x0, 2);
    DRV_MEM_REG_TCAM("Cid Tcam"      ,  DRV_FTM_CID_TCAM,   0, 32, 0x014d3000, 0xb0000000, 0x0, 3);
    #else
    DRV_MEM_REG_TCAM("LPM Tcam key0" ,  DRV_FTM_LPM_TCAM_KEY0,  0, 1024, 0x4100000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key1" ,  DRV_FTM_LPM_TCAM_KEY1,  1, 1024, 0x4104000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key2" ,  DRV_FTM_LPM_TCAM_KEY2,  2, 1024, 0x4108000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key3" ,  DRV_FTM_LPM_TCAM_KEY3,  3, 1024, 0x410c000, 0x0, 0x0, 1);

    DRV_MEM_REG_TCAM("LPM Tcam key4" ,  DRV_FTM_LPM_TCAM_KEY4,  4, 1024, 0x4120000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key5" ,  DRV_FTM_LPM_TCAM_KEY5,  5, 1024, 0x4124000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key6" ,  DRV_FTM_LPM_TCAM_KEY6,  6, 1024, 0x4128000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key7" ,  DRV_FTM_LPM_TCAM_KEY7,  7, 1024, 0x412c000, 0x0, 0x0, 1);

    DRV_MEM_REG_TCAM("LPM Tcam key8" ,  DRV_FTM_LPM_TCAM_KEY8,  8, 2048, 0x4140000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key9" ,  DRV_FTM_LPM_TCAM_KEY9,  9, 2048, 0x4148000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key10" , DRV_FTM_LPM_TCAM_KEY10, 10, 2048, 0x4150000, 0x0, 0x0, 1);
    DRV_MEM_REG_TCAM("LPM Tcam key11" , DRV_FTM_LPM_TCAM_KEY11, 11, 2048, 0x4158000, 0x0, 0x0, 1);


    DRV_MEM_REG("LPM Tcam Ad0" ,  DRV_FTM_LPM_TCAM_AD0,  1024, 0x4180000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad1" ,  DRV_FTM_LPM_TCAM_AD1,  1024, 0x4182000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad2" ,  DRV_FTM_LPM_TCAM_AD2,  1024, 0x4184000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad3" ,  DRV_FTM_LPM_TCAM_AD3,  1024, 0x4186000, 0x0, 0x0, 2, 0);

    DRV_MEM_REG("LPM Tcam Ad4" ,  DRV_FTM_LPM_TCAM_AD4,  1024, 0x4190000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad5" ,  DRV_FTM_LPM_TCAM_AD5,  1024, 0x4192000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad6" ,  DRV_FTM_LPM_TCAM_AD6,  1024, 0x4194000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad7" ,  DRV_FTM_LPM_TCAM_AD7,  1024, 0x4196000, 0x0, 0x0, 2, 0);

    DRV_MEM_REG("LPM Tcam Ad8" ,  DRV_FTM_LPM_TCAM_AD8,  2048, 0x41a0000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad9" ,  DRV_FTM_LPM_TCAM_AD9,  2048, 0x41a4000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad10" , DRV_FTM_LPM_TCAM_AD10, 2048, 0x41a8000, 0x0, 0x0, 2, 0);
    DRV_MEM_REG("LPM Tcam Ad11" , DRV_FTM_LPM_TCAM_AD11, 2048, 0x41ac000, 0x0, 0x0, 2, 0);

    DRV_MEM_REG_TCAM("Queue Tcam"    , DRV_FTM_QUEUE_TCAM, 0, 512, 0x00644000, 0xb1000000, 0x0, 3);
    DRV_MEM_REG_TCAM("Cid Tcam"      , DRV_FTM_CID_TCAM,   0, 128, 0x014d3000, 0xb0000000, 0x0, 2);
	#endif

    return 0;
}



int32
sys_tsingma_ftm_get_edram_bitmap(uint8 lchip,
                                     uint8 sram_type,
                                     uint32* bit)
{

    switch (sram_type)
    {
        /* SelEdram  Done */
        case DRV_FTM_SRAM_TBL_LPM_LKP_KEY0:
        bit[DRV_FTM_SRAM0] = 0;
        bit[DRV_FTM_SRAM3] = 1;
        bit[DRV_FTM_SRAM6]  = 2;
        bit[DRV_FTM_SRAM8]  = 3;
        break;

        /* SelEdram  {edram0, edram3, edram6, edram7} Done */
        case DRV_FTM_SRAM_TBL_LPM_LKP_KEY1:
        bit[DRV_FTM_SRAM1] = 0;
        bit[DRV_FTM_SRAM4] = 1;
        bit[DRV_FTM_SRAM7]  = 2;
        bit[DRV_FTM_SRAM10] = 3;
        break;

        /* SelEdram  Done */
        case DRV_FTM_SRAM_TBL_LPM_LKP_KEY2:
        bit[DRV_FTM_SRAM0] = 0;
        bit[DRV_FTM_SRAM3] = 1;
        bit[DRV_FTM_SRAM8]  = 2;
        break;

        /* SelEdram  {edram0, edram3, edram6, edram7} Done */
        case DRV_FTM_SRAM_TBL_LPM_LKP_KEY3:
        bit[DRV_FTM_SRAM1] = 0;
        bit[DRV_FTM_SRAM4] = 1;
        bit[DRV_FTM_SRAM10] = 2;
        break;


        /* SelEdram  {edram0, edram1, edram2, edram3, edram4, edram5 } Done*/
        case DRV_FTM_SRAM_TBL_MAC_HASH_KEY:
        bit[DRV_FTM_SRAM0] = 0;
        bit[DRV_FTM_SRAM1] = 1;
        bit[DRV_FTM_SRAM2] = 2;
        bit[DRV_FTM_SRAM3] = 3;
        bit[DRV_FTM_SRAM4] = 4;
        bit[DRV_FTM_SRAM5] = 5;

        bit[DRV_FTM_SRAM23] = DRV_USW_FTM_EXTERN_MEM_ID_BASE;
        bit[DRV_FTM_SRAM24] = DRV_USW_FTM_EXTERN_MEM_ID_BASE+1;
        bit[DRV_FTM_SRAM25] = DRV_USW_FTM_EXTERN_MEM_ID_BASE+2;
        bit[DRV_FTM_SRAM26] = DRV_USW_FTM_EXTERN_MEM_ID_BASE+3;

        break;

        /* SelEdram  {edram0, edram1, edram2, edram3, edram4, edram5 } Done*/
        case DRV_FTM_SRAM_TBL_FIB0_HASH_KEY:
        bit[DRV_FTM_SRAM0] = 0;
        bit[DRV_FTM_SRAM1] = 1;
        bit[DRV_FTM_SRAM2] = 2;
        bit[DRV_FTM_SRAM3] = 3;
        bit[DRV_FTM_SRAM4] = 4;
        bit[DRV_FTM_SRAM5] = 5;
        break;



        /* SelEdram  {edram11, edram12, edram13, edram14} Done*/
        case DRV_FTM_SRAM_TBL_DSMAC_AD:
        bit[DRV_FTM_SRAM11]   = 0;
        bit[DRV_FTM_SRAM12]   = 1;
        bit[DRV_FTM_SRAM13]   = 2;
        bit[DRV_FTM_SRAM14]   = 3;

        bit[DRV_FTM_SRAM27]   = DRV_USW_FTM_EXTERN_MEM_ID_BASE;
        bit[DRV_FTM_SRAM28]   = DRV_USW_FTM_EXTERN_MEM_ID_BASE+1;

        break;

        /* SelEdram  {edram11, edram12, edram13, edram14, edram16} Done*/
        case DRV_FTM_SRAM_TBL_DSIP_AD:
        bit[DRV_FTM_SRAM11]   = 0;
        bit[DRV_FTM_SRAM12]   = 1;
        bit[DRV_FTM_SRAM13]   = 2;
        bit[DRV_FTM_SRAM14]   = 3;
        bit[DRV_FTM_SRAM16]   = 4;

        bit[DRV_FTM_SRAM27]   = DRV_USW_FTM_EXTERN_MEM_ID_BASE;
        bit[DRV_FTM_SRAM28]   = DRV_USW_FTM_EXTERN_MEM_ID_BASE+1;
        break;


        /* SelEdram  {edram12, edram13, edram14, edram15, edram16} Done*/
        case DRV_FTM_SRAM_TBL_USERID_AD:
        bit[DRV_FTM_SRAM12]   = 0;
        bit[DRV_FTM_SRAM13]   = 1;
        bit[DRV_FTM_SRAM14]   = 2;
        bit[DRV_FTM_SRAM15]   = 3;
        bit[DRV_FTM_SRAM16]   = 4;
        break;


        /* SelEdram  {edram11, edram15, edram16} Done*/
        case DRV_FTM_SRAM_TBL_USERID_AD1:
        bit[DRV_FTM_SRAM11]   = 0;
        bit[DRV_FTM_SRAM15]   = 1;
        bit[DRV_FTM_SRAM16]   = 2;
        break;


        /* SelEdram  {edram16, edram18, edram19, edram21 } Done*/
        case DRV_FTM_SRAM_TBL_NEXTHOP:
        bit[DRV_FTM_SRAM17] = 0;
        bit[DRV_FTM_SRAM18] = 1;
        bit[DRV_FTM_SRAM19] = 2;
        bit[DRV_FTM_SRAM21] = 3;

        bit[DRV_FTM_SRAM29]   = DRV_USW_FTM_EXTERN_MEM_ID_BASE;


        break;

        /* SelEdram  {edram16, edram18, edram19, edram20, edram21 } Done*/
        case DRV_FTM_SRAM_TBL_MET:
        bit[DRV_FTM_SRAM17] = 0;
        bit[DRV_FTM_SRAM18] = 1;
        bit[DRV_FTM_SRAM19] = 2;
        bit[DRV_FTM_SRAM22] = 3;

        break;


        /* SelEdram  {edram18, edram19, edram20, edram21 } Done*/
    case DRV_FTM_SRAM_TBL_EDIT:
        bit[DRV_FTM_SRAM19] = 0;
        bit[DRV_FTM_SRAM21] = 1;
        bit[DRV_FTM_SRAM22] = 2;
        break;



        /* SelEdram  {edram17, edram18, edram19, edram20, edram21 } Done*/
        case DRV_FTM_SRAM_TBL_FWD:
        bit[DRV_FTM_SRAM18] = 0;
        bit[DRV_FTM_SRAM19] = 1;
        bit[DRV_FTM_SRAM20] = 2;
        bit[DRV_FTM_SRAM21] = 3;
        bit[DRV_FTM_SRAM22] = 3;
        break;


         /* SelEdram  {edram1, edram4} Done*/
        case DRV_FTM_SRAM_TBL_OAM_LM:
        bit[DRV_FTM_SRAM2] = 0;
        break;

         /* SelEdram  {edram1, edram4} Done*/
        case DRV_FTM_SRAM_TBL_OAM_MEP:
        bit[DRV_FTM_SRAM2] = 0;
        break;

         /* SelEdram  {edram1, edram4} Done*/
        case DRV_FTM_SRAM_TBL_OAM_MA:
        bit[DRV_FTM_SRAM2] = 0;
        break;

         /* SelEdram  {edram1, edram4} Done*/
        case DRV_FTM_SRAM_TBL_OAM_MA_NAME:
        bit[DRV_FTM_SRAM2] = 0;
        break;


            /* NONE*/
        case DRV_FTM_SRAM_TBL_FLOW_AD:
            bit[DRV_FTM_SRAM11]   = 0;
            break;


        /* NONE */
        case DRV_FTM_SRAM_TBL_FIB1_HASH_KEY:
        bit[DRV_FTM_SRAM9] = 0;
        bit[DRV_FTM_SRAM10] = 1;
        break;

            /* NONE */
        case DRV_FTM_SRAM_TBL_FLOW_HASH_KEY:
            bit[DRV_FTM_SRAM0] = 0;
            bit[DRV_FTM_SRAM1] = 1;
            break;

        /* NONE */
        case DRV_FTM_SRAM_TBL_XCOAM_HASH_KEY:
        bit[DRV_FTM_SRAM3] = 0;
        bit[DRV_FTM_SRAM4] = 1;
        break;

        /* NONE */
        case DRV_FTM_SRAM_TBL_USERID_HASH_KEY:
        bit[DRV_FTM_SRAM2] = 0;
        bit[DRV_FTM_SRAM6] = 1;
        bit[DRV_FTM_SRAM7] = 2;
        bit[DRV_FTM_SRAM8] = 3;
        bit[DRV_FTM_SRAM9] = 4;
        break;

        /* NONE */
        case DRV_FTM_SRAM_TBL_USERID1_HASH_KEY:
        bit[DRV_FTM_SRAM5] = 0;
        bit[DRV_FTM_SRAM8] = 1;
        bit[DRV_FTM_SRAM9] = 2;
        break;

        /* NONE */
        case DRV_FTM_SRAM_TBL_MPLS_HASH_KEY:
        bit[DRV_FTM_MIXED0] = 0;
        bit[DRV_FTM_MIXED1] = 1;
        break;

        case DRV_FTM_SRAM_TBL_MPLS_HASH_AD:
        bit[DRV_FTM_MIXED2] = 0;
        break;


        /* NONE */
        case DRV_FTM_SRAM_TBL_GEM_PORT:
        bit[DRV_FTM_MIXED2] = 0;
        bit[DRV_FTM_MIXED0] = 1;
        bit[DRV_FTM_MIXED1] = 2;

        break;



        default:
           break;
    }


    return DRV_E_NONE;
}

int32 drv_tsingma_get_mcu_lock_id(uint8 lchip, tbls_id_t tbl_id, uint8* p_mcu_id, uint32* p_lock_id)
{
    uint8  mcu_id  = 0xff;
    uint32 lock_id = DRV_MCU_LOCK_NONE;

    if((NULL == p_lock_id) || (NULL == p_mcu_id))
    {
        return DRV_E_INVALID_PTR;
    }

    switch(tbl_id)
    {
        case SharedPcsSoftRst0_t:
        case SharedPcsSoftRst1_t:
        case QsgmiiPcsSoftRst0_t:
        case QsgmiiPcsSoftRst1_t:
        case QsgmiiPcsSoftRst2_t:
        case QsgmiiPcsSoftRst3_t:
        case QsgmiiPcsSoftRst4_t:
        case QsgmiiPcsSoftRst5_t:
        case QsgmiiPcsSoftRst6_t:
        case QsgmiiPcsSoftRst7_t:
        case UsxgmiiPcsSoftRst0_t:
        case UsxgmiiPcsSoftRst1_t:
        case UsxgmiiPcsSoftRst2_t:
        case UsxgmiiPcsSoftRst3_t:
        case UsxgmiiPcsSoftRst4_t:
        case UsxgmiiPcsSoftRst5_t:
        case UsxgmiiPcsSoftRst6_t:
        case UsxgmiiPcsSoftRst7_t:
            lock_id = DRV_MCU_LOCK_PCS_RESET;
            mcu_id  = 0;
            break;
        case SharedPcsSoftRst2_t:
        case SharedPcsSoftRst3_t:
        case QsgmiiPcsSoftRst8_t:
        case QsgmiiPcsSoftRst9_t:
        case QsgmiiPcsSoftRst10_t:
        case QsgmiiPcsSoftRst11_t:
        case UsxgmiiPcsSoftRst8_t:
        case UsxgmiiPcsSoftRst9_t:
        case UsxgmiiPcsSoftRst10_t:
        case UsxgmiiPcsSoftRst11_t:
            lock_id = DRV_MCU_LOCK_PCS_RESET;
            mcu_id  = 1;
            break;
        case SharedPcsSoftRst4_t:
        case SharedPcsSoftRst5_t:
            lock_id = DRV_MCU_LOCK_PCS_RESET;
            mcu_id  = 2;
            break;
        case SharedPcsSoftRst6_t:
        case SharedPcsSoftRst7_t:
            lock_id = DRV_MCU_LOCK_PCS_RESET;
            mcu_id  = 3;
            break;
        default:
            break;
    }

    *p_mcu_id  = mcu_id;
    *p_lock_id = lock_id;

    return DRV_E_NONE;
}

int32 drv_tsingma_get_mcu_addr(uint8 mcu_id, uint32* mutex_data_addr, uint32* mutex_mask_addr)
{
    if((NULL == mutex_data_addr) || (NULL == mutex_mask_addr))
    {
        return DRV_E_INVALID_PTR;
    }

    switch(mcu_id)
    {
        case 0:
            *mutex_data_addr = TSINGMA_MCU_MUTEX0_CPU_DATA_0;
            *mutex_mask_addr = TSINGMA_MCU_MUTEX0_CPU_MASK_0;
            break;
        case 1:
            *mutex_data_addr = TSINGMA_MCU_MUTEX0_CPU_DATA_1;
            *mutex_mask_addr = TSINGMA_MCU_MUTEX0_CPU_MASK_1;
            break;
        case 2:
            *mutex_data_addr = TSINGMA_MCU_MUTEX0_CPU_DATA_2;
            *mutex_mask_addr = TSINGMA_MCU_MUTEX0_CPU_MASK_2;
            break;
        case 3:
            *mutex_data_addr = TSINGMA_MCU_MUTEX0_CPU_DATA_3;
            *mutex_mask_addr = TSINGMA_MCU_MUTEX0_CPU_MASK_3;
            break;
        default:
            return DRV_E_INVALID_TBL;
    }
    return DRV_E_NONE;
}

int32
drv_tsingma_chip_read_hss15g(uint8 lchip, uint8 hss_id, uint32 addr, uint16* p_data)
{
#ifdef EMULATION_ENV
#else
    uint8 rslt_lock = TRUE;
    int32 ret = 0;
    uint32 cmd = 0;
    uint32 tbl_id = 0;
    uint32 value = 0;
    uint32 timeout = 0x6400;
    uint8 acc_id = (uint8)((addr>>8) & 0xff);
    uint8 addr_raw = (uint8)(addr & 0xff);
    Hss12GRegAccCtl0_m acc_ctl;
    Hss12GRegAccResult0_m acc_rslt;

    /*uml donot care*/
    if (1 == SDK_WORK_PLATFORM)
    {
        return DRV_E_NONE;
    }

    DRV_PTR_VALID_CHECK(p_data);
    DRV_INIT_CHECK(lchip);

    sal_memset(&acc_ctl, 0, sizeof(Hss12GRegAccCtl0_m));

    ret = drv_usw_mcu_lock(lchip, DRV_MCU_LOCK_HSS15G_REG, hss_id);
    if(DRV_E_NONE != ret)
    {
        DRV_DBG_INFO("Get lock error (read 12G serdes reg)! hss_id=%u, addr=0x%x\n", hss_id, addr);
        return ret;
    }

    /* 1. write Hss12GRegAccCtl to run read action */
    tbl_id = Hss12GRegAccCtl0_t + hss_id;
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, Hss12GRegAccCtl0_hssAccValid_f, &value, &acc_ctl);
    value = acc_id;
    DRV_IOW_FIELD(lchip, tbl_id, Hss12GRegAccCtl0_hssAccId_f, &value, &acc_ctl);
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, Hss12GRegAccCtl0_hssAccIsRead_f, &value, &acc_ctl);
    value = addr_raw;
    DRV_IOW_FIELD(lchip, tbl_id, Hss12GRegAccCtl0_hssAccAddr_f, &value, &acc_ctl);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &acc_ctl);
    if (ret < 0)
    {
        drv_usw_mcu_unlock(lchip, DRV_MCU_LOCK_HSS15G_REG, hss_id);
        return DRV_E_ACCESS_HSS12G_FAIL;
    }

    /* 2. read Hss12GRegAccResult to get return value */
    value = 0;
    tbl_id = Hss12GRegAccResult0_t + hss_id;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    while(rslt_lock && (--timeout))
    {
        ret = DRV_IOCTL(lchip, 0, cmd, &acc_rslt);
        if (ret < 0)
        {
            drv_usw_mcu_unlock(lchip, DRV_MCU_LOCK_HSS15G_REG, hss_id);
            return DRV_E_ACCESS_HSS12G_FAIL;
        }
        DRV_IOR_FIELD(lchip, tbl_id, Hss12GRegAccResult0_hssAccAck_f, &value, &acc_rslt);
        if(1 == value)
        {
            rslt_lock = FALSE;
        }
    }
    if(TRUE == rslt_lock)
    {
        drv_usw_mcu_unlock(lchip, DRV_MCU_LOCK_HSS15G_REG, hss_id);
        return DRV_E_DATAPATH_READ_CHIP_FAIL;
    }
    DRV_IOR_FIELD(lchip, tbl_id, Hss12GRegAccResult0_hssAccAckData_f, &value, &acc_rslt);
    *p_data = (uint16)value;

    /* 3. clear Hss12GRegAccResultx.hssAccAck */
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, Hss12GRegAccResult0_hssAccAck_f, &value, &acc_rslt);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &acc_rslt);
    if (ret < 0)
    {
        drv_usw_mcu_unlock(lchip, DRV_MCU_LOCK_HSS15G_REG, hss_id);
        return DRV_E_ACCESS_HSS12G_FAIL;
    }

    ret = drv_usw_mcu_unlock(lchip, DRV_MCU_LOCK_HSS15G_REG, hss_id);
    if (DRV_E_NONE != ret)
    {
        DRV_DBG_INFO("Get unlock error (read 12G serdes reg)! hss_id=%u, addr=0x%x\n", hss_id, addr);
        return ret;
    }
#endif
    return DRV_E_NONE;
}

/**
 @brief access hss15g control register
*/
int32
drv_tsingma_chip_write_hss15g(uint8 lchip, uint8 hss_id, uint32 addr, uint16 data)
{
#ifdef EMULATION_ENV
#else
    uint8 rslt_lock = TRUE;
    int32 ret = 0;
    uint32 cmd = 0;
    uint32 tbl_id = 0;
    uint32 value = 0;
    uint32 timeout = 0x6400;
    uint8 acc_id = (uint8)((addr>>8) & 0xff);
    uint8 addr_raw = (uint8)(addr & 0xff);
    Hss12GRegAccCtl0_m acc_ctl;
    Hss12GRegAccResult0_m acc_rslt;

    /*uml donot care*/
    if (1 == SDK_WORK_PLATFORM)
    {
        return DRV_E_NONE;
    }

    DRV_INIT_CHECK(lchip);

    sal_memset(&acc_ctl, 0, sizeof(Hss12GRegAccCtl0_m));

    ret = drv_usw_mcu_lock(lchip, DRV_MCU_LOCK_HSS15G_REG, hss_id);
    if(DRV_E_NONE != ret)
    {
        DRV_DBG_INFO("Get lock error (write 12G serdes reg)! hss_id=%u, addr=0x%x, data=%u\n", hss_id, addr, data);
        return ret;
    }

    /* 1. write Hss12GRegAccCtl to run write action */
    tbl_id = Hss12GRegAccCtl0_t + hss_id;
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, Hss12GRegAccCtl0_hssAccValid_f, &value, &acc_ctl);
    value = acc_id;
    DRV_IOW_FIELD(lchip, tbl_id, Hss12GRegAccCtl0_hssAccId_f, &value, &acc_ctl);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, Hss12GRegAccCtl0_hssAccIsRead_f, &value, &acc_ctl);
    value = data;
    DRV_IOW_FIELD(lchip, tbl_id, Hss12GRegAccCtl0_hssAccWdata_f, &value, &acc_ctl);
    value = addr_raw;
    DRV_IOW_FIELD(lchip, tbl_id, Hss12GRegAccCtl0_hssAccAddr_f, &value, &acc_ctl);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &acc_ctl);
    if (ret < 0)
    {
        drv_usw_mcu_unlock(lchip, DRV_MCU_LOCK_HSS15G_REG, hss_id);
        return DRV_E_ACCESS_HSS12G_FAIL;
    }

    /* 2. read Hss12GRegAccResult to get return value */
    value = 0;
    tbl_id = Hss12GRegAccResult0_t + hss_id;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    while(rslt_lock && (--timeout))
    {
        ret = DRV_IOCTL(lchip, 0, cmd, &acc_rslt);
        if (ret < 0)
        {
            drv_usw_mcu_unlock(lchip, DRV_MCU_LOCK_HSS15G_REG, hss_id);
            return DRV_E_ACCESS_HSS12G_FAIL;
        }
        DRV_IOR_FIELD(lchip, tbl_id, Hss12GRegAccResult0_hssAccAck_f, &value, &acc_rslt);
        if(1 == value)
        {
            rslt_lock = FALSE;
        }
    }
    if(TRUE == rslt_lock)
    {
        drv_usw_mcu_unlock(lchip, DRV_MCU_LOCK_HSS15G_REG, hss_id);
        return DRV_E_DATAPATH_READ_CHIP_FAIL;
    }

    /* 3. clear Hss12GRegAccResultx.hssAccAck */
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, Hss12GRegAccResult0_hssAccAck_f, &value, &acc_rslt);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &acc_rslt);
    if (ret < 0)
    {
        drv_usw_mcu_unlock(lchip, DRV_MCU_LOCK_HSS15G_REG, hss_id);
        return DRV_E_ACCESS_HSS12G_FAIL;
    }

    ret = drv_usw_mcu_unlock(lchip, DRV_MCU_LOCK_HSS15G_REG, hss_id);
    if (DRV_E_NONE != ret)
    {
        DRV_DBG_INFO("Get unlock error (write 12G serdes reg)! hss_id=%u, addr=0x%x, data=%u\n", hss_id, addr, data);
        return ret;
    }
#endif
    return DRV_E_NONE;
}

/**
 @brief access hss28g control register
*/
int32
drv_tsingma_chip_read_hss28g(uint8 lchip, uint8 hss_id, uint32 addr, uint16* p_data)
{
#ifdef EMULATION_ENV
#else
    uint8 rslt_lock = TRUE;
    int32 ret = 0;
    uint32 cmd = 0;
    uint32 tbl_id = 0;
    uint32 value = 0;
    uint32 timeout = 0x6400;
    Hss28GRegAccCtl_m acc_ctl;
    Hss28GRegAccResult_m acc_rslt;

    /*uml donot care*/
    if (1 == SDK_WORK_PLATFORM)
    {
        return DRV_E_NONE;
    }

    DRV_PTR_VALID_CHECK(p_data);
    DRV_INIT_CHECK(lchip);

    sal_memset(&acc_ctl, 0, sizeof(Hss28GRegAccCtl_m));

    /* 1. write Hss28GRegAccCtl to run read action */
    tbl_id = Hss28GRegAccCtl_t;
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, Hss28GRegAccCtl_hssAccValid_f, &value, &acc_ctl);
    value = hss_id;
    DRV_IOW_FIELD(lchip, tbl_id, Hss28GRegAccCtl_hssAccId_f, &value, &acc_ctl);
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, Hss28GRegAccCtl_hssAccIsRead_f, &value, &acc_ctl);
    value = addr;
    DRV_IOW_FIELD(lchip, tbl_id, Hss28GRegAccCtl_hssAccAddr_f, &value, &acc_ctl);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &acc_ctl);
    if (ret < 0)
    {
        return DRV_E_ACCESS_HSS12G_FAIL;
    }

    /* 2. read Hss28GRegAccResult to get return value */
    value = 0;
    tbl_id = Hss28GRegAccResult_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    while(rslt_lock && (--timeout))
    {
        ret = DRV_IOCTL(lchip, 0, cmd, &acc_rslt);
        if (ret < 0)
        {
            return DRV_E_ACCESS_HSS12G_FAIL;
        }
        DRV_IOR_FIELD(lchip, tbl_id, Hss28GRegAccResult_hssAccAck_f, &value, &acc_rslt);
        if(1 == value)
        {
            rslt_lock = FALSE;
        }
    }

    DRV_IOR_FIELD(lchip, tbl_id, Hss28GRegAccResult_hssAccAckError_f, &value, &acc_rslt);
    if((1 == value) || (TRUE == rslt_lock))
    {
        return DRV_E_DATAPATH_READ_CHIP_FAIL;
    }
    DRV_IOR_FIELD(lchip, tbl_id, Hss28GRegAccResult_hssAccAckData_f, &value, &acc_rslt);
    *p_data = (uint16)value;

    /* 3. clear Hss12GRegAccResultx.hssAccAck */
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, Hss28GRegAccResult_hssAccAck_f, &value, &acc_rslt);
    DRV_IOW_FIELD(lchip, tbl_id, Hss28GRegAccResult_hssAccAckError_f, &value, &acc_rslt);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &acc_rslt);
    if (ret < 0)
    {
        return DRV_E_ACCESS_HSS12G_FAIL;
    }
#endif
    return DRV_E_NONE;
}

/**
 @brief access hss28g control register
*/
int32
drv_tsingma_chip_write_hss28g(uint8 lchip, uint8 hss_id, uint32 addr, uint16 data)
{
#ifdef EMULATION_ENV
#else
    uint8  rslt_lock = TRUE;
    int32  ret       = 0;
    uint32 cmd       = 0;
    uint32 tbl_id    = 0;
    uint32 value     = 0;
    uint32 timeout   = 0x6400;
    Hss28GRegAccCtl_m acc_ctl;
    Hss28GRegAccResult_m acc_rslt;

    /*uml donot care*/
    if (1 == SDK_WORK_PLATFORM)
    {
        return DRV_E_NONE;
    }

    DRV_INIT_CHECK(lchip);

    sal_memset(&acc_ctl, 0, sizeof(Hss28GRegAccCtl_m));

    /* 1. write Hss28GRegAccCtl to run write action */
    tbl_id = Hss28GRegAccCtl_t;
    value = 1;
    DRV_IOW_FIELD(lchip, tbl_id, Hss28GRegAccCtl_hssAccValid_f, &value, &acc_ctl);
    value = hss_id;
    DRV_IOW_FIELD(lchip, tbl_id, Hss28GRegAccCtl_hssAccId_f, &value, &acc_ctl);
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, Hss28GRegAccCtl_hssAccIsRead_f, &value, &acc_ctl);
    value = data;
    DRV_IOW_FIELD(lchip, tbl_id, Hss28GRegAccCtl_hssAccWdata_f, &value, &acc_ctl);
    value = addr;
    DRV_IOW_FIELD(lchip, tbl_id, Hss28GRegAccCtl_hssAccAddr_f, &value, &acc_ctl);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &acc_ctl);
    if (ret < 0)
    {
        return DRV_E_ACCESS_HSS12G_FAIL;
    }

    /* 2. read Hss28GRegAccResult to get return value */
    value = 0;
    tbl_id = Hss28GRegAccResult_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    while(rslt_lock && (--timeout))
    {
        ret = DRV_IOCTL(lchip, 0, cmd, &acc_rslt);
        if (ret < 0)
        {
            return DRV_E_ACCESS_HSS12G_FAIL;
        }
        DRV_IOR_FIELD(lchip, tbl_id, Hss28GRegAccResult_hssAccAck_f, &value, &acc_rslt);
        if(1 == value)
        {
            rslt_lock = FALSE;
        }
    }
    DRV_IOR_FIELD(lchip, tbl_id, Hss28GRegAccResult_hssAccAckError_f, &value, &acc_rslt);
    if((1 == value) || (TRUE == rslt_lock))
    {
        return DRV_E_DATAPATH_READ_CHIP_FAIL;
    }

    /* 3. clear Hss28GRegAccResultx.hssAccAck */
    value = 0;
    DRV_IOW_FIELD(lchip, tbl_id, Hss28GRegAccResult_hssAccAck_f, &value, &acc_rslt);
    DRV_IOW_FIELD(lchip, tbl_id, Hss28GRegAccResult_hssAccAckError_f, &value, &acc_rslt);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, 0, cmd, &acc_rslt);
    if (ret < 0)
    {
        return DRV_E_ACCESS_HSS12G_FAIL;
    }
#endif
    return DRV_E_NONE;
}

int32
drv_enum_init_tsingma(uint8 lchip)
{
    DRV_CONST(DRV_IPFIX_EXPORTREASON_NO_EXPORT)                  = 0x0;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_EXPIRED)                    = 0x1;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_TCP_SESSION_CLOSE)          = 0x2;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_PACKET_COUNT_OVERFLOW)      = 0x3;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_BYTE_COUNT_OVERFLOW)        = 0x4;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_NEW_FLOW_EXPORT)            = 0x5;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_DESTINATION_CHANGE)         = 0x6;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_TS_COUNT_OVERFLOW)          = 0x7;

    DRV_CONST(DRV_DS_CATEGORY_ID_PAIR_TCAM_LOOKUP_KEY_BYTES) = 4;
    DRV_CONST(DRV_TCAMKEYTYPE_MACKEY_160)               = 0x0;
    DRV_CONST(DRV_TCAMKEYTYPE_L3KEY_160)                = 0x1;
    DRV_CONST(DRV_TCAMKEYTYPE_L3KEY_320)                = 0x2;
    DRV_CONST(DRV_TCAMKEYTYPE_IPV6KEY_320)              = 0x3;
    DRV_CONST(DRV_TCAMKEYTYPE_IPV6KEY_640)              = 0x4;
    DRV_CONST(DRV_TCAMKEYTYPE_MACL3KEY_320)             = 0x6;
    DRV_CONST(DRV_TCAMKEYTYPE_MACL3KEY_640)             = 0xe;
    DRV_CONST(DRV_TCAMKEYTYPE_MACIPV6KEY_640)           = 0x7;
    DRV_CONST(DRV_TCAMKEYTYPE_CIDKEY_160)               = 0x8;
    DRV_CONST(DRV_TCAMKEYTYPE_SHORTKEY_80)              = 0x9;
    DRV_CONST(DRV_TCAMKEYTYPE_FORWARDKEY_320)           = 0xa;
    DRV_CONST(DRV_TCAMKEYTYPE_FORWARDKEY_640)           = 0xb;
    DRV_CONST(DRV_TCAMKEYTYPE_COPPKEY_320)              = 0xc;
    DRV_CONST(DRV_TCAMKEYTYPE_COPPKEY_640)              = 0xd;
    DRV_CONST(DRV_TCAMKEYTYPE_UDFKEY_320)               = 0x5;
    DRV_CONST(DRV_XC_OAM_HASH_CAM_NUM)      = 128;

    /*DRV_CONST(DRV_SCL_KEY_TYPE_L2KEY);*/
    /*DRV_CONST(DRV_SCL_KEY_TYPE_L3KEY) ;*/
    /*DRV_CONST(DRV_SCL_KEY_TYPE_L2L3KEY) ;*/
    DRV_CONST(DRV_SCL_KEY_TYPE_MACKEY160)               = 0x0;
    DRV_CONST(DRV_SCL_KEY_TYPE_MACL3KEY320)             = 0x3;
    DRV_CONST(DRV_SCL_KEY_TYPE_L3KEY160)                = 0x1;
    DRV_CONST(DRV_SCL_KEY_TYPE_IPV6KEY320)              = 0x2;
    DRV_CONST(DRV_SCL_KEY_TYPE_MACIPV6KEY640)           = 0x7;
    DRV_CONST(DRV_SCL_KEY_TYPE_RESOLVE_CONFLICT)        = 0x5;
    DRV_CONST(DRV_SCL_KEY_TYPE_UDFKEY160)               = 0x6;
    DRV_CONST(DRV_SCL_KEY_TYPE_UDFKEY320)               = 0x4;

    DRV_CONST(DRV_SCL_KEY_TYPE_MASK)                    = 0x7;


    DRV_CONST(DRV_UDFPOSTYPE_OUTER_L2)                = 0x0;
    DRV_CONST(DRV_UDFPOSTYPE_OUTER_L3)                = 0x1;
    DRV_CONST(DRV_UDFPOSTYPE_OUTER_L4)                = 0x2;
    DRV_CONST(DRV_UDFPOSTYPE_NONE)                    = 0x3;
   /* DRV_CONST(DRV_UDFPOSTYPE_INNER_L2); */
   /* DRV_CONST(DRV_UDFPOSTYPE_INNER_L3); */
   /* DRV_CONST(DRV_UDFPOSTYPE_INNER_L4); */
   /* DRV_CONST(DRV_UDFPOSTYPE_RSV); */
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_DISABLE )             = 0x0;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_DOUBLEVLANPORT)       = 0x1;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_SVLANPORT)            = 0x2;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_CVLANPORT)            = 0x3;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_SVLANCOSPORT)         = 0x4;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_CVLANCOSPORT)         = 0x5;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_PORTVLANCROSS)        = 0x6;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_PORTCROSS)            = 0x7;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_PORT)                 = 0x8;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_SVLANPORTMAC)         = 0x9;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_TUNNELPBB)            = 0xa;

    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_ETH)                  = 0x10;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_BFD)                  = 0x11;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_MPLSLABEL)            = 0x12;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_MPLSSECTION)          = 0x13;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_RMEP)                 = 0x14;

    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_FCOE)             = 0x0;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV4)             = 0x1;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV6MCAST)        = 0x2;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV6UCAST)        = 0x3;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_MAC)              = 0x4;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_MACIPV6MCAST)     = 0x5;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_TRILL)            = 0x6;


    DRV_CONST(DRV_FIBHOST1PRIMARYHASHTYPE_IPV4)             = 0x0;
    DRV_CONST(DRV_FIBHOST1PRIMARYHASHTYPE_IPV6NATDA)        = 0x1;
    DRV_CONST(DRV_FIBHOST1PRIMARYHASHTYPE_IPV6NATSA)        = 0x2;
    DRV_CONST(DRV_FIBHOST1PRIMARYHASHTYPE_OTHER)            = 0x3;

    DRV_CONST(DRV_FLOWHASHTYPE_INVALID)                     = 0x0;
    DRV_CONST(DRV_FLOWHASHTYPE_L2)                          = 0x1;
    DRV_CONST(DRV_FLOWHASHTYPE_L2L3)                        = 0x2;
    DRV_CONST(DRV_FLOWHASHTYPE_L3IPV4)                      = 0x3;
    DRV_CONST(DRV_FLOWHASHTYPE_L3IPV6)                      = 0x4;
    DRV_CONST(DRV_FLOWHASHTYPE_L3MPLS)                      = 0x5;

    DRV_CONST(DRV_USERIDHASHTYPE_DISABLE)                   = 0x0;
    DRV_CONST(DRV_USERIDHASHTYPE_DOUBLEVLANPORT)            = 0x1;
    DRV_CONST(DRV_USERIDHASHTYPE_SVLANPORT)                 = 0x2;
    DRV_CONST(DRV_USERIDHASHTYPE_CVLANPORT)                 = 0x3;
    DRV_CONST(DRV_USERIDHASHTYPE_SVLANCOSPORT)              = 0x4;
    DRV_CONST(DRV_USERIDHASHTYPE_CVLANCOSPORT)              = 0x5;
    DRV_CONST(DRV_USERIDHASHTYPE_MACPORT)                   = 0x6;
    DRV_CONST(DRV_USERIDHASHTYPE_IPV4PORT)                  = 0x7;
    DRV_CONST(DRV_USERIDHASHTYPE_MAC)                       = 0x8;
    DRV_CONST(DRV_USERIDHASHTYPE_IPV4SA)                    = 0x9;
    DRV_CONST(DRV_USERIDHASHTYPE_PORT)                      = 0xa;
    DRV_CONST(DRV_USERIDHASHTYPE_SVLANMACSA)                = 0xb;
    DRV_CONST(DRV_USERIDHASHTYPE_SVLAN)                     = 0xc;
    DRV_CONST(DRV_USERIDHASHTYPE_ECIDNAMESPACE)             = 0xd;
    DRV_CONST(DRV_USERIDHASHTYPE_INGECIDNAMESPACE)          = 0xe;
    DRV_CONST(DRV_USERIDHASHTYPE_IPV6SA)                    = 0xf;
    DRV_CONST(DRV_USERIDHASHTYPE_IPV6PORT)                  = 0x10;



    DRV_CONST(DRV_USERIDHASHTYPE_CAPWAPSTASTATUS)           = 0x11;
    DRV_CONST(DRV_USERIDHASHTYPE_CAPWAPSTASTATUSMC)         = 0x12;
    DRV_CONST(DRV_USERIDHASHTYPE_CAPWAPMACDAFORWARD)        = 0x13;
    DRV_CONST(DRV_USERIDHASHTYPE_CAPWAPVLANFORWARD)         = 0x14;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4)                = 0x15;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTYPE_START)         = DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4);
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4GREKEY)          = 0x16;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UDP)             = 0x17;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELPBB)                 = 0x18;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLUCRPF)          = 0x19;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLUCDECAP)        = 0x1a;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLMCRPF)          = 0x1b;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLMCDECAP)        = 0x1c;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLMCADJ)          = 0x1d;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4RPF)             = 0x1e;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UCVXLANMODE0)    = 0x1f;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UCVXLANMODE1)    = 0x20;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UCVXLANMODE0)    = 0x21;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UCVXLANMODE1)    = 0x22;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UCNVGREMODE0)    = 0x23;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UCNVGREMODE1)    = 0x24;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UCNVGREMODE0)    = 0x25;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UCNVGREMODE1)    = 0x26;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4MCVXLANMODE0)    = 0x27;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4VXLANMODE1)      = 0x28;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6MCVXLANMODE0)    = 0x29;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6MCVXLANMODE1)    = 0x2a;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4MCNVGREMODE0)    = 0x2b;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4NVGREMODE1)      = 0x2c;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6MCNVGREMODE0)    = 0x2d;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6MCNVGREMODE1)    = 0x2e;


    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4CAPWAP)          = 0x2f;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6CAPWAP)          = 0x30;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELCAPWAPRMAC)          = 0x31;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELCAPWAPRMACRID)       = 0x32;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELMPLS)                = 0x34;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6)                = 0x33;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6GREKEY)          = 0x34;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UDP)             = 0x35;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6DA)              = 0x36;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4DA)              = 0x37;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTYPE_END)        = DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4DA);


    DRV_CONST(DRV_USERIDHASHTYPE_SCLFLOWL2)                 = 0x38;
    DRV_CONST(DRV_USERIDHASHTYPE_SCLFLOWTYPE_END)        = DRV_CONST(DRV_USERIDHASHTYPE_SCLFLOWL2);


    DRV_CONST(DRV_USERIDPORTHASHTYPE_DISABLE)              = 0x0;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_DOUBLEVLANPORT)       = 0x1;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANPORT)            = 0x2;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_CVLANPORT)            = 0x3;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANCOSPORT)         = 0x4;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_CVLANCOSPORT)         = 0x5;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_MACPORT)              = 0x6;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_IPSAPORT)             = 0x7;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_MAC)                  = 0x8;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_IPSA)                 = 0x9;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_PORT)                 = 0xa;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANMACSA)           = 0xb;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLAN)                = 0xc;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_ECIDNAMESPACE)        = 0xd;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_INGECIDNAMESPACE)     = 0xe;

    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANDSCPPORT)        = 0xf;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SCLTYPE_END)         = DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANDSCPPORT) ;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_TUNNEL)               = 0x1d;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SCLFLOW)              = 0x1e;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_TRILL)                = 0x1f;



    DRV_CONST(DRV_STK_MUX_TYPE_HDR_REGULAR_PORT)      = 0x0;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITHOUT_TUNNEL)    = 0x7;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_L2)           = 0x8;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_L2_AND_IPV4)  = 0xF;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_L2_AND_IPV6)  = 0xF;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_IPV4)         = 0xF;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_IPV6)         = 0xF;


    DRV_CONST(DRV_DMA_PACKET_TX_CHAN_NUM) = 4;
    DRV_CONST(DRV_DMA_PACKET_RX_CHAN_NUM) = 4;
    DRV_CONST(DRV_DMA_PACKET_RX0_CHAN_ID) = 0;
    DRV_CONST(DRV_DMA_PACKET_RX1_CHAN_ID) = 1;
    DRV_CONST(DRV_DMA_PACKET_RX2_CHAN_ID) = 2;
    DRV_CONST(DRV_DMA_PACKET_RX3_CHAN_ID) = 3;
    DRV_CONST(DRV_DMA_PACKET_TX0_CHAN_ID) = 4;
    DRV_CONST(DRV_DMA_PACKET_TX1_CHAN_ID) = 5;
    DRV_CONST(DRV_DMA_PACKET_TX2_CHAN_ID) = 6;
    DRV_CONST(DRV_DMA_PACKET_TX3_CHAN_ID) = 7;
    DRV_CONST(DRV_DMA_TBL_RD_CHAN_ID)     = 8;
    DRV_CONST(DRV_DMA_PORT_STATS_CHAN_ID) = 9;
    DRV_CONST(DRV_DMA_FLOW_STATS_CHAN_ID) = 10;
    DRV_CONST(DRV_DMA_BUF_SCAN_CHAN_ID)   = 0xFF;
    DRV_CONST(DRV_DMA_REG_MAX_CHAN_ID)    = 11;
    DRV_CONST(DRV_DMA_TBL_RD1_CHAN_ID)    = 12;
    DRV_CONST(DRV_DMA_TBL_RD2_CHAN_ID)    = 13;
    DRV_CONST(DRV_DMA_TBL_WR_CHAN_ID)     = 14;
    DRV_CONST(DRV_DMA_LEARNING_CHAN_ID)   = 15;
    DRV_CONST(DRV_DMA_HASHKEY_CHAN_ID)    = 16;
    DRV_CONST(DRV_DMA_IPFIX_CHAN_ID)      = 17;
    DRV_CONST(DRV_DMA_SDC_CHAN_ID)        = 18;
    DRV_CONST(DRV_DMA_MONITOR_CHAN_ID)    = 19;

    DRV_CONST(DRV_DMA_TCAM_SCAN_DESC_NUM) = 37;
    DRV_CONST(DRV_DMA_PKT_TX_TIMER_CHAN_ID) = 7;
    /*DRV_CONST(DRV_DMA_MAX_CHAN_ID);*/

    DRV_CONST(DRV_FLOWPORTTYPE_BITMAP)                      = 0x0;
    DRV_CONST(DRV_FLOWPORTTYPE_GPORT)                       = 0x1;
    DRV_CONST(DRV_FLOWPORTTYPE_LPORT)                       = 0x2;
    DRV_CONST(DRV_FLOWPORTTYPE_METADATA)                    = 0x3;















    DRV_CONST(DRV_VTAGACTIONTYPE_NONE)                      = 0x0;
    DRV_CONST(DRV_VTAGACTIONTYPE_MODIFY)                    = 0x1;
    DRV_CONST(DRV_VTAGACTIONTYPE_ADD)                       = 0x2;
    DRV_CONST(DRV_VTAGACTIONTYPE_DELETE)                    = 0x3;

    DRV_CONST(DRV_GEMHASHTYPE_PORT)                         = 0x1;

    DRV_CONST(DRV_IPFIXHASHTYPE_INVALID)                    = 0x0;
    DRV_CONST(DRV_IPFIXHASHTYPE_L2)                         = 0x1;
    DRV_CONST(DRV_IPFIXHASHTYPE_L2L3)                       = 0x2;
    DRV_CONST(DRV_IPFIXHASHTYPE_L3IPV4)                     = 0x3;
    DRV_CONST(DRV_IPFIXHASHTYPE_L3IPV6)                     = 0x4;
    DRV_CONST(DRV_IPFIXHASHTYPE_L3MPLS)                     = 0x5;

    DRV_CONST(DRV_MPLSHASHTYPE_LABEL)                       = 0x0;

    DRV_CONST(DRV_OAMHASHTYPE_ETH)                          = 0x0;
    DRV_CONST(DRV_OAMHASHTYPE_BFD)                          = 0x1;
    DRV_CONST(DRV_OAMHASHTYPE_MPLSLABEL)                    = 0x2;
    DRV_CONST(DRV_OAMHASHTYPE_MPLSSECTION)                  = 0x3;
    DRV_CONST(DRV_OAMHASHTYPE_RMEP)                         = 0x4;

    DRV_CONST(DRV_FIBHOST0HASHTYPE_FCOE)                    = 0x0;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_IPV4)                    = 0x1;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_IPV6MCAST)               = 0x2;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_IPV6UCAST)               = 0x3;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_MAC)                     = 0x4;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_MACIPV6MCAST)            = 0x5;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_TRILL)                   = 0x6;

    DRV_CONST(DRV_FIBHOST1HASHTYPE_FCOERPF)                 = 0x0;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4MCAST)               = 0x1;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4NATDAPORT)           = 0x2;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4NATSAPORT)           = 0x3;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6MCAST)               = 0x4;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6NATDAPORT)           = 0x5;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6NATSAPORT)           = 0x6;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_MACIPV4MCAST)            = 0x7;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_MACIPV6MCAST)            = 0x8;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_TRILLMCASTVLAN)          = 0x9;
    DRV_CONST(DRV_FIB_HOST0_CAM_NUM)        = 32;
    DRV_CONST(DRV_FIB_HOST1_CAM_NUM)        = 32;
    DRV_CONST(DRV_FLOW_HASH_CAM_NUM)        = 32;
    DRV_CONST(DRV_USER_ID_HASH_CAM_NUM)     = 0;
    DRV_CONST(DRV_MPLS_HASH_CAM_NUM)        = 64;
    DRV_CONST(DRV_OAM_HASH_CAM_NUM)         = 64;
    DRV_CONST(DRV_RMEP_HASH_CAM_NUM)        = 32;
    DRV_CONST(DRV_GEM_PORT_HASH_CAM_NUM)    = 64;


    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4DA) = 0x37;
    DRV_CONST(DRV_USERIDHASHTYPE_SCLFLOWL2) = 0x38;




























    DRV_CONST(DRV_MAX_LPM_TCAM_NUM)       = 12;
    DRV_CONST(DRV_MAX_NOR_TCAM_NUM)       = 19;
    DRV_CONST(DRV_EPE_DISCARD_TYPE_NUM)   = 56;
    DRV_CONST(DRV_KEY_METADATA_BITS)      = 14;

    DRV_CONST(DRV_PARSER_L4_TYPE_UDP)       = 2;
    DRV_CONST(DRV_PARSER_L4_TYPE_GRE)       = 3;
    DRV_CONST(DRV_PARSER_L4_TYPE_TCP)       = 1;
    DRV_CONST(DRV_PARSER_L4_USER_TYPE_UDP_VXLAN)    = 5;

    DRV_CONST(DRV_EGRACL_L3K160_SHAREFIELDS_L4PORT_RNG_BMP) = 0;
    DRV_CONST(DRV_EGRACL_L3K160_SHAREFIELDS_DEFAULT)        = 3;

    DRV_CONST(DRV_DIAG_MAC_HASH_WIDTH)      = 85;
    DRV_CONST(DRV_DIAG_IPV4_HASH_WIDTH)     = 85;
    DRV_CONST(DRV_DIAG_MPLS_HASH_WIDTH)     = 34;
    DRV_CONST(DRV_DIAG_OAM_MEP_WIDTH)       = 170;
    DRV_CONST(DRV_DIAG_APS_WIDTH)           = 163;
    DRV_CONST(DRV_DIAG_FLEX_TCAM_WIDTH)     = 80;
    DRV_CONST(DRV_DIAG_EDIT_WIDTH)          = 90;

    DRV_CONST(DRV_ACCREQ_ADDR_HOST0) = 0x08050e4c;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_HOST0) = 30;
    DRV_CONST(DRV_ACCREQ_ADDR_FIB) = 0x08022230;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_FIB) = 8;
    DRV_CONST(DRV_ACCREQ_ADDR_USERID) = 0x08001930;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_USERID) = 3;
    DRV_CONST(DRV_ACCREQ_ADDR_EGRESSXCOAM) = 0x08011d2c;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_EGRESSXCOAM) = 0;
    DRV_CONST(DRV_ACCREQ_ADDR_CIDPAIR) = 0x014d4fbc;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_CIDPAIRHASH) = 0;
    DRV_CONST(DRV_ACCREQ_ADDR_MPLS) = 0x01d40b04;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_MPLS) = 2;
    DRV_CONST(DRV_ACCREQ_ADDR_GEMPORT) = 0x01d40b30;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_GEMPORT) = 22;

    DRV_CONST(DRV_OAM_MEPTYPE_ETH_CCM_MEP)       =0x0;
    DRV_CONST(DRV_OAM_MEPTYPE_PBT_CCM_MEP)       =0x1;
    DRV_CONST(DRV_OAM_MEPTYPE_TRILL_BFD_MEP)     =0x2;
    DRV_CONST(DRV_OAM_MEPTYPE_FFD_MEP)           =0x3;
    DRV_CONST(DRV_OAM_MEPTYPE_CV1_MEP)           =0x4;
    DRV_CONST(DRV_OAM_MEPTYPE_BFD_MEP)           =0x5;
    DRV_CONST(DRV_OAM_MEPTYPE_ACH_Y1731_MEP)     =0x6;
    DRV_CONST(DRV_OAM_MEPTYPE_ACH_BFD_MEP)       =0x7;

    DRV_CONST(DRV_DsDesc_done_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_done_f_START_BIT) = 31;
    DRV_CONST(DRV_DsDesc_done_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_u1_pkt_sop_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_u1_pkt_sop_f_START_BIT) = 0;
    DRV_CONST(DRV_DsDesc_u1_pkt_sop_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_u1_pkt_eop_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_u1_pkt_eop_f_START_BIT) = 1;
    DRV_CONST(DRV_DsDesc_u1_pkt_eop_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_memAddr_f_START_WORD) = 2;
    DRV_CONST(DRV_DsDesc_memAddr_f_START_BIT) = 4;
    DRV_CONST(DRV_DsDesc_memAddr_f_BIT_WIDTH) = 28;
    DRV_CONST(DRV_DsDesc_realSize_f_START_WORD) = 1;
    DRV_CONST(DRV_DsDesc_realSize_f_START_BIT) = 16;
    DRV_CONST(DRV_DsDesc_realSize_f_BIT_WIDTH) = 16;
    DRV_CONST(DRV_DsDesc_cfgSize_f_START_WORD) = 1;
    DRV_CONST(DRV_DsDesc_cfgSize_f_START_BIT) = 0;
    DRV_CONST(DRV_DsDesc_cfgSize_f_BIT_WIDTH) = 16;
    DRV_CONST(DRV_DsDesc_dataStruct_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_dataStruct_f_START_BIT) = 8;
    DRV_CONST(DRV_DsDesc_dataStruct_f_BIT_WIDTH) = 6;
    DRV_CONST(DRV_DsDesc_reserved0_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_reserved0_f_START_BIT) = 7;
    DRV_CONST(DRV_DsDesc_reserved0_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_error_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_error_f_START_BIT) = 28;
    DRV_CONST(DRV_DsDesc_error_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_chipAddr_f_START_WORD) = 3;
    DRV_CONST(DRV_DsDesc_chipAddr_f_START_BIT) = 0;
    DRV_CONST(DRV_DsDesc_chipAddr_f_BIT_WIDTH) = 32;
    DRV_CONST(DRV_DsDesc_pause_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_pause_f_START_BIT) = 17;
    DRV_CONST(DRV_DsDesc_pause_f_BIT_WIDTH) = 1;

    DRV_CONST(DRV_HOST0_SINGLE_KEY_BYTE) = 12;
    DRV_CONST(DRV_HOST0_DOUBLE_KEY_BYTE) = 24;
    DRV_CONST(DRV_HOST0_QUAD_KEY_BYTE)   = 48;
    DRV_CONST(DRV_NAT_TCAM_AGING_BASE) = 8192;

    DRV_CONST(DRV_MIRROR_INGRESS_L2SPAN_DISCARD) = 0x1;
    DRV_CONST(DRV_MIRROR_INGRESS_L3SPAN_DISCARD) = 0x2;
    DRV_CONST(DRV_MIRROR_INGRESS_ACLLOG_PRI_DISCARD) = 0x3FC;
    DRV_CONST(DRV_MIRROR_INGRESS_IPFIX_MIRROR_DISCARD) = 0x800;
    DRV_CONST(DRV_MIRROR_EGRESS_L2SPAN_DISCARD) = 0x1;
    DRV_CONST(DRV_MIRROR_EGRESS_L3SPAN_DISCARD) = 0x2;
    DRV_CONST(DRV_MIRROR_EGRESS_ACLLOG_PRI_DISCARD) = 0x1C;
    DRV_CONST(DRV_MIRROR_EGRESS_IPFIX_MIRROR_DISCARD) = 0x40;
    return 0;
}

extern int32
drv_tm_ftm_api_init(uint8 lchip);

drv_io_tcam_db_t drv_tsingma_io_tcam_db[DRV_IO_TCAM_TYPE_NUM] = {
/*FLOW*/  {11,    DRV_BYTES_PER_ENTRY,        FlowTcamTcamMem_t,      FlowTcamTcamMem_tcamEntryValid_f, 8, DRV_FTM_TCAM_KEY0},
/*LPM*/   {13,    DRV_LPM_KEY_BYTES_PER_ENTRY,LpmTcamTcamMem_t,       LpmTcamTcamMem_tcamEntryValid_f,  4, DRV_FTM_LPM_TCAM_KEY0},
/*NAT*/   {13,    DRV_LPM_KEY_BYTES_PER_ENTRY,LpmTcamTcamMem_t,       LpmTcamTcamMem_tcamEntryValid_f,  4, DRV_FTM_LPM_TCAM_KEY8},
/*ACL0*/  {0,     0,                          0,                      0,                                0, 0},
/*ACL1*/  {0,     0,                          0,                      0,                                0, 0},
/*SCL0*/  {0,     0,                          0,                      0,                                0, 0},
/*SCL1*/  {0,     0,                          0,                      0,                                0, 0},
/*SCL2*/  {0,     0,                          0,                      0,                                0, 0},
/*CID*/   {0,     4,                          IpeCidTcamMem_t,        IpeCidTcamMem_tcamEntryValid_f,   2, DRV_FTM_CID_TCAM},
/*QUE*/   {0,     12,                         QMgrEnqTcamMem_t,       QMgrEnqTcamMem_tcamEntryValid_f,  8, DRV_FTM_QUEUE_TCAM},
/*LTID*/  {0,     0,                          0,                      0,                                0, 0},
/*VMAC*/  {0,     0,                          0,                      0,                                0, 0},
/*UDF*/   {0,     0,                          0,                      0,                                0, 0}
};

/**
 @brief get flow tcam blknum and local index
*/
STATIC  int32
drv_tm_tcam_get_blknum_index(uint8 lchip, tbls_id_t tbl_id, uint32 index, uint32 *blknum, uint32 *local_idx)
{
    *local_idx = index;
    *blknum = TCAM_KEY_BLOCK_ID(lchip, tbl_id, 0);

    return DRV_E_NONE;
}

STATIC  int32
drv_tm_nat_tcam_get_blknum_index(uint8 lchip, tbls_id_t tbl_id, uint32 index, uint32 *blknum, uint32 *local_idx)
{
    *local_idx = p_drv_master[lchip]->lpm_index_map[2] ? p_drv_master[lchip]->lpm_index_map[2][index]: index;
    *blknum = TCAM_KEY_BLOCK_ID(lchip, tbl_id, 0);

    return DRV_E_NONE;
}
STATIC  int32
drv_flow_tcam_get_blknum_index(uint8 lchip, tbls_id_t tbl_id, uint32 index, uint32 *blknum, uint32 *local_idx)
{

    if (index < DRV_MEM_ENTRY_NUM(lchip,TCAM_KEY_BLOCK_ID(lchip, tbl_id, 0)+DRV_FTM_TCAM_KEY0))
    {
        *blknum = TCAM_KEY_BLOCK_ID(lchip, tbl_id, 0);
        *local_idx = p_drv_master[lchip]->p_mem_info[*blknum+DRV_FTM_TCAM_KEY0].index_map ? \
            p_drv_master[lchip]->p_mem_info[*blknum+DRV_FTM_TCAM_KEY0].index_map[index] : \
            index;
    }
    else
    {
        *blknum = TCAM_KEY_BLOCK_ID(lchip, tbl_id, 1);
        *local_idx = p_drv_master[lchip]->p_mem_info[*blknum+DRV_FTM_TCAM_KEY0].index_map ? \
            p_drv_master[lchip]->p_mem_info[*blknum+DRV_FTM_TCAM_KEY0].index_map[(index - DRV_MEM_ENTRY_NUM(lchip,(TCAM_KEY_BLOCK_ID(lchip, tbl_id, 0)+DRV_FTM_TCAM_KEY0)))] : \
            (index - DRV_MEM_ENTRY_NUM(lchip,(TCAM_KEY_BLOCK_ID(lchip, tbl_id, 0)+DRV_FTM_TCAM_KEY0)));
    }

    return DRV_E_NONE;
}

static drv_mchip_sdb_t drv_sdb_api =
{
    drv_sdb_store
};

int32
drv_tbls_list_init_tsingma(uint8 lchip)
{
    uint8 i = 0;
    uint16 tbl_idx = 0;

    p_drv_master[lchip]->p_tbl_ext_info = (tables_ext_info_t*)mem_malloc(MEM_SYSTEM_MODULE, (MaxTblId_t+1)*sizeof(tables_ext_info_t));
    if(!p_drv_master[lchip]->p_tbl_ext_info)
    {
        return -1;
    }
    sal_memset(p_drv_master[lchip]->p_tbl_ext_info, 0, (MaxTblId_t+1)*sizeof(tables_ext_info_t));

    p_drv_master[lchip]->p_tbl_mapping = (uint16*)mem_malloc(MEM_SYSTEM_MODULE, MaxTblId_t*sizeof(uint16));
    if(!p_drv_master[lchip]->p_tbl_mapping)
    {
        return -1;
    }

    p_drv_master[lchip]->p_tbl_info = drv_tm_tbls_list;
    for (tbl_idx = 0; tbl_idx < MaxTblId_t; tbl_idx++)
    {
        p_drv_master[lchip]->p_tbl_mapping[tbl_idx] = (sizeof(drv_tm_tbls_list)/sizeof(tables_info_t) -1);
    }
    for (tbl_idx = 0; tbl_idx < (sizeof(drv_tm_tbls_list)/sizeof(tables_info_t) - 1); tbl_idx++)
    {
        p_drv_master[lchip]->p_tbl_mapping[p_drv_master[lchip]->p_tbl_info[tbl_idx].tbl_id] = tbl_idx;
    }

    p_drv_master[lchip]->p_mem_info = (drv_mem_t*)mem_malloc(MEM_SYSTEM_MODULE, DRV_FTM_MAX_ID*sizeof(drv_mem_t));
    if(NULL == p_drv_master[lchip]->p_mem_info)
    {
        return -1;
    }
    sal_memset(p_drv_master[lchip]->p_mem_info, 0, DRV_FTM_MAX_ID*sizeof(drv_mem_t));
    p_drv_master[lchip]->drv_io_tcam_db = drv_tsingma_io_tcam_db;

#ifndef DRV_DS_LITE
    p_drv_master[lchip]->p_tbl_name = drv_tm_tbls_name_list;
#endif

    for (i = 0; i < DRV_IO_TCAM_TYPE_NUM; i++)
    {
        p_drv_master[lchip]->drv_io_tcam_db[i].drv_tcam_get_block_info = drv_tm_tcam_get_blknum_index;

#if (1 == SDK_WORK_PLATFORM)
        p_drv_master[lchip]->drv_io_tcam_db[i].hw_words = drv_tsingma_io_tcam_db[i].tcam_mem_tbl_id? TABLE_INFO(lchip, drv_tsingma_io_tcam_db[i].tcam_mem_tbl_id).byte/4:0;
#endif
    }

    p_drv_master[lchip]->drv_io_tcam_db[DRV_IO_TCAM_TYPE_NAT].drv_tcam_get_block_info = drv_tm_nat_tcam_get_blknum_index;
    p_drv_master[lchip]->drv_io_tcam_db[DRV_IO_TCAM_TYPE_FLOW].drv_tcam_get_block_info = drv_flow_tcam_get_blknum_index;

    p_drv_master[lchip]->drv_ecc_data.p_intr_tbl = drv_ecc_tm_err_intr_tbl;
    p_drv_master[lchip]->drv_ecc_data.p_sbe_cnt  = drv_ecc_tm_sbe_cnt;
    p_drv_master[lchip]->drv_ecc_data.p_scan_tcam_tbl = drv_ecc_tm_scan_tcam_tbl;

    drv_mem_init_tsingma(lchip);


    p_drv_master[lchip]->drv_mem_get_edram_bitmap = sys_tsingma_ftm_get_edram_bitmap;

    p_drv_master[lchip]->drv_get_mcu_lock_id = drv_tsingma_get_mcu_lock_id;
    p_drv_master[lchip]->drv_get_mcu_addr = drv_tsingma_get_mcu_addr;

    p_drv_master[lchip]->drv_chip_read_hss15g = drv_tsingma_chip_read_hss15g;
    p_drv_master[lchip]->drv_chip_write_hss15g = drv_tsingma_chip_write_hss15g;
    p_drv_master[lchip]->drv_chip_read_hss28g = drv_tsingma_chip_read_hss28g;
    p_drv_master[lchip]->drv_chip_write_hss28g = drv_tsingma_chip_write_hss28g;
    p_drv_master[lchip]->mchip_api.p_mchip_sdb = &drv_sdb_api;

    p_drv_master[lchip]->p_enum_value = drv_tm_enum;
    p_drv_master[lchip]->p_tcam_map = drv_tm_tcam_mem_map;
    drv_enum_init_tsingma(lchip);

    drv_tm_ftm_api_init(lchip);

    return 0;
}


int32
drv_tbls_list_deinit_tsingma(uint8 lchip)
{
    if(p_drv_master[lchip]->p_tbl_ext_info)
    {
        mem_free(p_drv_master[lchip]->p_tbl_ext_info);
    }
    if(p_drv_master[lchip]->p_tbl_mapping)
    {
        mem_free(p_drv_master[lchip]->p_tbl_mapping);
    }
    return 0;
}


#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_C
#undef DRV_DEF_E
#undef DRV_DEF_SDK_F
#undef DRV_DEF_SDK_D


#endif



